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參數(shù)資料
| 型號： | AD7538JN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT W/BUFF 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時間： | 1.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1W |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 667k |
AD7538
Rev. B | Page 10 of 16
CIRCUIT INFORMATION
EQUIVALENT CIRCUIT ANALYSIS
Figure 5 shows an equivalent circuit for the analog section
of the AD7538 DAC. The current source ILEAKAGE is composed
of surface and junction leakages. The RO resistor denotes the
equivalent output resistance of the DAC, which varies with
input code. COUT is the capacitance due to the current steering
switches and varies from about 90 pF to 180 pF (typical values)
depending upon the digital input. g(VREF, N) is the Thevenin
equivalent voltage generator due to the reference input voltage,
VREF, and the transfer function of the DAC ladder, N.
ILEAKAGE
COUT
IOUT
AGND
RFB
RO
R/4
g (VREF, N)
01
13
9-
00
5
Figure 5. AD7538 Equivalent Analog Output Circuit
DIGITAL SECTION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close as possible to 0 V and 5 V logic levels.
UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
Figure 6 shows the circuit diagram for unipolar binary
operation. With an ac input, the circuit performs 2-quadrant
multiplication. The code table for Figure 6 is given in Table 6.
Capacitor C1 provides phase compensation and helps prevent
overshoot and ringing when high-speed op amps are used.
619
5
24
23
1
20
21
22
2
3
4
DB13 TO DB0 DGND
VDD
VREF
VIN
RFB
IOUT
VDD
VO
–15V
AGND
VSS
LDAC
CS
WR
LDAC
CS
WR
AD7538
A1
R3
1k
R2
10
R1
20
R4
47k
INPUT DATA
DIGITAL
GND
C2
4.7F
C1
33pF
ANALOG
GND
AD711
01
13
9-
0
06
+
Figure 6. Unipolar Binary Operation
Table 6. Unipolar Binary Code Table
Binary Number In
DAC Register
Analog Output, VOUT
MSB
LSB
11 1111 1111 1111
VIN(16,383/16,384)
10 0000 0000 0000
VIN(8192/16,384) = VIN
00 0000 0000 0001
VIN(1/16,384)
00 0000 0000 0000
0 V
For zero offset adjustment, the DAC register is loaded with
all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V.
Adjusting VOUT to 0 V is not necessary in many applications,
but it is recommended that VOS be no greater than (25 × 106)
Hints section).
Full-scale trimming is accomplished by loading the DAC
register with all 1s and adjusting R1 so that VOUTA = VIN
(16,383/16,384). For high temperature operation, resistors
and potentiometers should have a low temperature coefficient.
In many applications, because of the excellent gain TC and
gain error specifications of the AD7538, gain error trimming is
not necessary. In fixed reference applications, full scale can also
be adjusted by omitting R1 and R2 and trimming the reference
voltage magnitude.
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