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參數(shù)資料
| 型號(hào)： | AD7538JN |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT W/BUFF 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 1.5µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1W |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 667k |
AD7538
Rev. B | Page 11 of 16
BIPOLAR OPERATION (4-QUADRANT
MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 8. Offset binary coding is used. The code table
With the DAC loaded to 10 0000 0000 0000, adjust R1 for VO =
0 V. Alternatively, one can omit R1 and R2 and adjust the ratio
of R5 and R6 for VO = 0 V. Full-scale trimming can be accom-
plished by adjusting the amplitude of VIN or by varying the
value of R7.
The values given for R1, R2 are the minimum necessary to
calibrate the system for Resistors R5, R6, R7 ratio matched to
0.1%. System linearity error is independent of resistor ratio
matching and is affected by DAC linearity error only.
When operating over a wide temperature range, it is important
that the resistors be of the same type so that their temperature
coefficients match.
LOW LEAKAGE CONFIGURATION
For CMOS multiplying DAC, as the device is operated at higher
temperatures, the output leakage current increases. For a 14-bit
resolution system, this can be a significant source of error. The
AD7538 features a leakage reduction configuration to keep the
leakage current low over an extended temperature range. One
may operate the device with or without this configuration. If VSS
(Pin 24) is tied to AGND then the DAC exhibits normal output
leakage currents at high temperatures. To use the low leakage
facility, VSS should be tied to a voltage of approximately 0.3 V
as in Figure 6 and Figure 8. A simple resistor divider (R3, R4)
produces approximately 300 mV from 15 V. The C2
capacitor in parallel with R3 is an integral part of the low
leakage configuration and must be 4.7 μF or greater. Figure 7
is a plot of leakage current vs. temperature for both conditions.
It clearly shows the improvement gained by using the low
leakage configuration.
Table 7. Bipolar Code Table for the Offset Binary Circuit
of Figure 8
Binary Number In
DAC Register
Analog Output VOUT
MSB
LSB
11 1111 1111 1111
+VIN(8191/8192)
10 0000 0000 0001
+VIN(1/8192)
10 0000 0000 0000
0 V
01 1111 1111 1111
VIN(1/8192)
00 0000 0000 0000
VIN(8191/8192)
30
40
50
60
70
80
90
100 110 120
TEMPERATURE (°C)
L
E
AKA
G
E
CURR
E
NT
(n
A)
60
50
40
30
20
10
0
VDD = 15V
VREF = 10V
VSS = 0V
VSS = –0.3V
0
1
13
9-
0
08
Figure 7. Graph of Typical Leakage Current vs. Temperature for AD7538
619
5
24
23
1
20
21
22
2
3
4
DB13 TO DB0 DGND
VDD
VREF
RFB
IOUT
VDD
–15V
AGND
VSS
LDAC
CS
WR
LDAC
CS
WR
AD7538
A1
R3
1k
R2
22
R5
10k
R7
20k
R6
20k
R8
5k, 10%
R1
50
R4
47k
INPUT DATA
DIGITAL
GND
C2
4.7F
C1
33pF
ANALOG
GND
AD711
A2
AD711
01
13
9-
00
7
VIN
VO
+
Figure 8. Bipolar Operation
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