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| 型號(hào)： | AD7541AKPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT MONO 20PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
AD7541A
–3–
REV. B
ABSOLUTE MAXIMUM RATINGS*
(TA = +25
°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25 V
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25 V
Digital Input Voltage to GND . . . . . . . . –0.3 V, VDD + 0.3 V
OUT 1, OUT 2 to GND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package)
To +75
°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above +75
°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
TERMINOLOGY
RELATIVE ACCURACY
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is expressed in % of full-
scale range or (sub)multiples of 1 LSB.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal l LSB change between any two adjacent
codes. A specified differential nonlinearity of
±1 LSB max over
the operating temperature range insures monotonicity.
GAIN ERROR
Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is
–
4095
4096
(VREF ).
Gain error is adjustable to zero using external trims as shown in
Figures 4, 5 and 6.
OUTPUT LEAKAGE CURRENT
Current which appears at OUTI with the DAC loaded to all 0s
or at OUT2 with the DAC loaded to all 1s.
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from VREF terminal to
OUT1 with DAC loaded to all 0s.
OUTPUT CURRENT SETTLING TIME
Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full
scale.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = GND and a Model 50K as the
output op amp, C1 (phase compensation) = 0 pF.
Operating Temperature Range
Commercial (J, K Versions) . . . . . . . . . . . . . 0
°C to +70°C
Industrial (A, B Versions) . . . . . . . . . . . . . –25
°C to +85°C
Extended (S, T Versions) . . . . . . . . . . . . . –55
°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP/SOIC
LCCC
PLCC
14
13
12
11
17
16
15
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7541A
OUT1
BIT 12 (LSB)
VDD (+)
VREF IN
RFEEDBACK
OUT2
GND
BIT 1 (MSB)
BIT 9
BIT 10
BIT 11
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
20 19
1
2
3
OUT
2
OUT
1
NC
R
FB
V
REF
BIT
5
BIT
6
18
14
15
16
17
4
5
6
7
8
9 1011 1213
TOP VIEW
(Not to Scale)
AD7541A
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
VDD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
NC = NO CONNECT
NC
BIT
7
BIT
8
20 19
18
1
2
3
4
5
6
7
8
910
11 12 13
14
15
16
17
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
VDD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
NC = NO CONNECT
OUT
2
OUT
1
NC
R
FB
V
REF
AD7541A
BIT
5
BIT
6
NC
BIT
7
BIT
8
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