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參數(shù)資料
| 型號(hào)： | AD7541AKPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT MONO 20PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
AD7541A
–6–
REV. B
APPLICATIONS HINTS
Output Offset: CMOS D/A converters exhibit a code-dependent
output resistance which in turn can cause a code-dependent
error voltage at the output of the amplifier. The maximum am-
plitude of this offset, which adds to the D/A converter nonlin-
earity, is 0.67 VOS where VOS is the amplifier input offset
voltage. To maintain monotonic operation it is recommended
that VOS be no greater than (25
× 10–6) (V
REF) over the tempera-
ture range of operation. Suitable op amps are AD517L and
AD544L. The AD517L is best suited for fixed reference appli-
cations with low bandwidth requirements: it has extremely low
offset (50
V) and in most applications will not require an offset
trim. The AD544L has a much wider bandwidth and higher
slew rate and is recommended for multiplying and other appli-
cations requiring fast settling. An offset trim on the AD544L
may be necessary in some circuits.
Digital Glitches: One cause of digital glitches is capacitive
coupling from the digital lines to the OUT1 and OUT2 termi-
nals. This should be minimized by screening the analog pins of
the AD7541A (Pins 1, 2, 17, 18) from the digital pins by a
ground track run between Pins 2 and 3 and between Pins 16
and 17 of the AD7541A. Note how the analog pins are at one
end of the package and separated from the digital pins by VDD
and GND to aid screening at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital-to-analog
sections of the AD7541A, particularly in circuits with high cur-
rents and fast rise and fall times.
Temperature Coefficients: The gain temperature coefficient
of the AD7541A has a maximum value of 5 ppm/
°C and a typi-
cal value of 2 ppm/
°C. This corresponds to worst case gain shifts
of 2 LSBs and 0.8 LSBs, respectively, over a 100
°C temperature
range. When trim resistors R1 and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note “Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs,” Publication Number
E630c-5-3/86.
SINGLE SUPPLY OPERATION
Figure 7 shows the AD7541A connected in a voltage switching
mode. OUT1 is connected to the reference voltage and OUT2
is connected to GND. The D/A converter output voltage is
available at the VREF pin (Pin 17) and has a constant output
impedance equal to RLDR. The feedback resistor RFB is not used
in this circuit.
1
2
PINS 4–15
AD7541A
RFB
VREF
GND
OUT1
OUT2
BIT 1 – BIT 12
16
18
17
3
NOT
USED
VDD
VOUT = 0V TO +10V
R2
30k
R1
10k
SYSTEM
GROUND
V+
V–
CA3140B
VDD = +15V
VREF
+2.5V
VOUT ±VREF D (1 +R2/R1) WHERE 0 ≤ D ≤ 1
i.e., D IS A FRACTIONAL REPRESENTATION OF THE DIGITAL INPUT
15
4
Figure 7. Single Supply Operation Using Voltage Switch-
ing Mode
The reference voltage must always be positive. If OUT1 goes
more than 0.3 V less than GND, an internal diode will be turned
on and a heavy current may flow causing device damage (the
AD7541A is, however, protected from the SCR latch-up
phenomenon prevalent in many CMOS devices). Suitable refer-
ences include the AD580 and AD584.
The loading on the reference voltage source is code-dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.
To maintain linearity, the voltage at OUT1 should remain within
2.5 V of GND, for a VDD of 15 V. If VDD is reduced from 15 V
or the reference voltage at OUT1 increased to more than 2.5 V,
the differential nonlinearity of the DAC will increase and the
linearity of the DAC will be degraded.
SUPPLEMENTAL APPLICATION MATERIAL
For further information on CMOS multiplying D/A converters,
the reader is referred to the following texts:
CMOS DAC Application Guide, Publication Number
G872b-8-1/89 available from Analog Devices.
Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACs Application Note, Publication Number
E630c-5-3/86 available from Analog Devices.
Analog-Digital Conversion Handbook—available from Analog
Devices.
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