參數(shù)資料
型號： AD7568BP
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： EB Melody & Chime Series; Mounting Style: Panel mount; Functions: Melody & Chime; Rated Voltage: 120V AC; Style: Box style; Color: Beige Enclosure; Diameter: 133mm square; Applicable Model: EB
中文描述： OCTAL, SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 12-BIT DAC, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 3/12頁
文件大小： 241K
代理商： AD7568BP
AD7568
REV. B
–3–
TIMNGSPECIFICATIONS
Limit at
T
A
= +25
8
C
Limit at
T
A
= –40
8
C to +85
8
C
Parameter
Units
Description
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
82
t
9
100
40
40
30
30
5
90
70
40
100
40
40
30
30
5
90
70
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
CLK IN Cycle T ime
CLK IN High T ime
CLK IN Low T ime
FSIN
Setup T ime
Data Setup T ime
Data Hold T ime
FSIN
Hold T ime
SDOUT Valid After CLK IN Falling Edge
LDAC
,
CLR
Pulse Width
NOT ES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
8
is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
CLKIN (I)
SDIN (I)
SDOUT (O)
DB15
DB0
DB15
DB0
FSIN (I)
LDAC, CLR
t
1
t
4
t
7
t
2
t
3
t
6
t
5
t
8
t
9
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
(V
DD
= +5 V
6
5%; I
OUT1
= I
OUT2
= 0 V; T
A
= T
MN
to T
MAX
, unless otherwse noted)
1.6mA
I
OL
+2.1V
I
OH
200
μ
A
C
L
50pF
TO OUTPUT
PIN
Figure 2. Load Circuit for Digital Output
Timing Specifications
ORDE RING GUIDE
T emperature
Range
Linearity
E rror (LSBs)
Package
Option*
Model
AD7568BS
AD7568BP
–40
°
C to +85
°
C
–40
°
C to +85
°
C
±
0.5
±
0.5
S-44
P-44A
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
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