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參數(shù)資料
| 型號： | AD7621ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 265K |
| 代理商： | AD7621ACP |
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–23–
External Discontinuous Clock Data Read After Con-
version
Though the maximum throughput cannot be achieved
using this mode, it is the most recommended of the serial
slave modes. Figure 20 shows the detailed timing dia-
grams of this method. After a conversion is complete,
indicated by BUSY returning low, the result of this con-
version can be read while both
CS
and
RD
are low. The
data is shifted out, MSB first, with 16 clock pulses and is
valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion
process.
Another advantage is to be able to read the data at any
speed up to 80 MHz which accommodates both slow
digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7621 provides a
“daisy-chain” feature using the RDC/SDIN input pin for
cascading multiple converters together. This feature is
useful for reducing component count and wiring connec-
tions when desired as, for instance, in isolated
multiconverter applications.
An example of the concatenation of two devices is shown
in Figure 21. Simultaneous sampling is possible by using
a common
CNVST
signal. It should be noted that the
RDC/SDIN input is latched on the edge of SCLK oppo-
site to the one used to shift out the data on SDOUT.
Hence, the MSB of the “upstream” converter just follows
the LSB of the “downstream” converter on the next
SCLK cycle.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X
1
X0
Y15
Y14
CS
BUSY
SDIN
EXT/INT = 1
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15
X14
X
1
2
18
RD = 0
17
16
15
3
Figure 20. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
CS
SCLK
D1
D0
X
D15
D14
D15
1
2
16
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/INT = 1
INVSCLK = 0
RD =0
3
15
4
Figure 22. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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| AD7621ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 3Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
| AD7621ACPZ | 功能描述:IC ADC 16BIT 2MSPS DIFF 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7621ACPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 2 LSB INL, 3 MSPS PulSAR?? ADC |
| AD7621ACPZRL | 功能描述:IC ADC 16BIT 2MSPS DIFF 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7621ACPZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 2 LSB INL, 3 MSPS PulSAR?? ADC |
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