CREF
參數(shù)資料
型號(hào)： AD7621ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/32頁(yè)
文件大小： 0K
描述： IC ADC 16BIT 2MSPS DIFF 48LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 2M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 86mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，雙極
AD7621
Rev. 0 | Page 4 of 32
Parameter
Conditions
Min
Typ
Max
Unit
Turn-On Settling Time
CREF = 10 μF
5
ms
REFBUFIN Output Voltage
REFBUFIN @ 25°C
1.2
V
REFBUFIN Output Resistance
6.33
kΩ
EXTERNAL REFERENCE
PDREF = PDBUF = high
Voltage Range
REF
1.8
2.048
AVDD
V
Current Drain
3 MSPS throughput
250
μA
REFERENCE BUFFER
PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range
1.05
1.2
1.30
V
TEMPERATURE PIN
Voltage Output
@ 25°C
273
mV
Temperature Sensitivity
0.85
mV/°C
Output Resistance
4.7
kΩ
DIGITAL INPUTS
Logic Levels
VIL
–0.3
+0.6
V
VIH
1.7
5.25
V
IIL
–1
+1
μA
IIH
–1
+1
μA
DIGITAL OUTPUTS
Data Format7
Pipeline Delay8
VOL
ISINK = 500 μA
0.4
V
VOH
ISOURCE = –500 μA
OVDD 0.3
V
POWER SUPPLIES
Specified Performance
AVDD
2.37
2.5
2.63
V
DVDD
2.37
2.5
2.63
V
OVDD
2.309
3.6
V
Operating Current10
3 MSPS throughput
AVDD11
With internal reference
25.2
mA
DVDD
3.6
mA
OVDD
1
mA
Power Dissipation11
With Internal Reference10
3 MSPS throughput
70
86
mW
Without Internal Reference10
3 MSPS throughput
65
80
mW
With Internal Reference 12
1.25 MSPS throughput
42
55
mW
Without Internal Reference12
1.25 MSPS throughput
37
50
mW
In Power-Down Mode13
PD = high
600
μW
TEMPERATURE RANGE14
Specified Performance
TMIN to TMAX
–40
+85
°C
1 When using an external reference. With the internal reference, the input range is 0.1 V to VREF.
2 See the Analog Inputs section.
3 Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.
4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.
5 See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7 Parallel or serial 16-bit.
8 Conversion results are available immediately after completed conversion.
10 In warp mode. Tested in parallel reading mode.
11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12 In impulse mode. Tested in parallel reading mode.
13 With all digital inputs forced to OVDD.
14 Consult factory for extended temperature range.
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