參數(shù)資料
型號： AD7621AST
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝： MO-026-BBC, LQFP-48
文件頁數(shù)： 2/26頁
文件大小： 265K
代理商： AD7621AST
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621–SPECIFICATIONS
–2–
(–40 C to +85 C, V
REF
= AVDD, AVDD = DVDD = OVDD = 2.5 V, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT
Complete Cycle In WideBand Warp Mode
Throughput Rate In Wideband Warp Mode
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
Gain Error, T
MIN
to T
MAX2
Gain Error Temperature Drift
Zero Error, T
MIN
to T
MAX2
Zero Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
16
Bits
V
IN+
– V
IN-
V
IN+,
V
IN-
to AGND
f
= TBD kHz
TBD MSPS Throughput
-V
REF
–0.1
+V
AVDD
V
V
dB
μ A
TBD
T B D
See Analog Input Section
SPEED
333
3
3
1
500
2
800
1.25
ns
MSPS
MSPS
ms
ns
MSPS
ns
MSPS
0.1
0.001
In Warp Mode
In Warp Mode
In Normal Mode
In Normal Mode
In Impulse Mode
In Impulse Mode
0
0
– 1
– 1
16
± 1
+ 1
+ 1
LSB
1
L S B
Bits
L S B
% of FSR
ppm/°C
LSB
ppm/°C
L S B
V
REF
= AVDD
0.7
±TBD
±TBD
±TBD
±TBD
± T B D
±TBD
AVDD = 2.5V ± 5%
f
IN
= 100 kHz,
V
REF
=AVDD
V
REF
=2.048V
f
IN
= 100 kHz
f
IN
= 100 kHz
f
IN
= 100 kHz,
f
IN
= 100 kHz,–60 dB Input
88
90
88.3
100
–100
90
30
50
dB
3
d B
d B
d B
d B
d B
M H z
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
–3 dB Input Bandwidth
SAMPLING
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage recovery
REFERENCE
External Reference Voltage Range
REF Current Drain
REF Voltage with reference buffer
Reference Buffer Input Voltage
REFBUFIN Input Current
INTERNAL
REFERENCE
Internal Reference Voltage
Internal Reference Temp Drift
Internal Reference Temp Drift
REFBUFIN Line Regulation
REFBUFIN Output Resistance
Power Supply Rejection
Turn-on Settling Time
Long-term Stability
Hysterisis
REFBUFIN Output Resistance
Temperature Pin Voltage Output
Temperature Sensitivity
TEMP pin Output Resistance
DYNAMICS
1
TBD
ns
ps rms
ns
ns
Full-Scale Step
50
50
R E F
3 MSPS Throughput
REFBUFIN=1.2V
REFBUFIN
T B D
2.048
T B D
2.048
1.2
AVDD
V
μ A
V
V
μ A
2
T B D
– 1
2.1
T B D
+ 1
@ 25 C
–40 C to +85 C
0 C to +70 C
AVDD = 2.5V ± 5%
TBD
1.2
TBD
TBD
TBD
16
TBD
TBD
TBD
TBD
TBD
313
1
4.3
TBD
V
ppm/ C
ppm/ C
ppm/V
k
dB
μs
ppm
ppm
k
m V
mV/ C
k
@ TBD kHz
1,000 Hours
@ 25 C
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