參數(shù)資料
型號: AD7621AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: MO-026-BBC, LQFP-48
文件頁數(shù): 24/26頁
文件大?。?/td> 265K
代理商: AD7621AST
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–24–
CNVST
CS
SCLK
SDOUT
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7621
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7621
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
Figure 21. Two AD7621s in a “Daisy-Chain” Configuration
External Clock Data Read During Conversion
Figure 22 shows the detailed timing diagrams of this
method. During a conversion, while both
CS
and
RD
are
both low, the result of the previous conversion can be
read. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the
clock. The 16 bits have to be read before the current con-
version is complete. If that is not done, RDERROR is
pulsed high and can be used to interrupt the host inter-
face to prevent incomplete data reading. There is no
“daisy chain” feature in this mode and RDC/SDIN
input should always be tied either high or low.
To reduce performance degradation due to digital activity,
a fast discontinuous clock of is recommended to ensure that
all the bits are read during the first half of the conversion
phase. It is also possible to begin to read the data after
conversion and continue to read the last bits even after a new
conversion has been initiated.
MICROPROCESSOR INTERFACING
The AD7621 is ideally suited for traditional dc measure-
ment applications supporting a microprocessor, and ac
signal processing applications interfacing to a digital sig-
nal processor. The AD7621 is designed to interface either
with a parallel 8-bit or 16-bit wide interface or with a
general purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used
with the AD7621 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of
the AD7621 with an SPI equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 22 shows an interface diagram between the
AD7621 and an SPI-equipped DSP, ADSP219x. To
accommodate the slower speed of the DSP, the AD7621
acts as a slave device and data must be read after conver-
sion. This mode also allows the “daisy chain” feature.
The convert command could be initiated in response to an
internal timer interrupt. The reading process could be
initiated in response to the end-of-conversion signal
(BUSY going low) using an interrupt line of the DSP.
The Serial Peripheral Interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI interrupt enable (TIMOD) =00 by writing to the SPI
Control Register (SPICLTx). It should be noted that to
meet all timing requirements, the SPI clock should be
limited to 17Mbits/s which allow to read an ADC result
in about 1.1
s. When higher sampling rate is desired, it
is recomended to use one of the parallel interface mode
with the ADSP-219x.
SPIxSEL (PFx)
ADSP-219x*
CNVST
AD7621*
CS
MISOx
SCKx
PFx or TFSx
SDOUT
SCLK
INVSCLK
EXT/INT
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SER/PAR
RD
PFx
BUSY
Figure 23. Interfacing the AD7621 to SPI Interface
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