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參數資料
| 型號： | AD7622BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DIFFERENTL 48-LFCSP |
| 標準包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數： | 16 |
| 采樣率（每秒）： | 2M |
| 數據接口： | 串行，并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 85mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7622CBZ-ND - BOARD EVALUATION FOR AD7622 |
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AD7622
Rev. 0 | Page 20 of 28
Temperature Sensor
The TEMP pin measures the temperature of the AD7622. To
improve the calibration accuracy over the temperature range,
the output of the TEMP pin is applied to one of the inputs of
the analog switch (such as, ADG779), and the ADC itself is
used to measure its own temperature. This configuration is
shown in Figure 29.
ADG779
AD8021
CC
ANALOG INPUT
(UNIPOLAR)
AD7622
IN+
TEMPERATURE
SENSOR
TEMP
060
23-
027
Figure 29. Use of the Temperature Sensor
POWER SUPPLY
The AD7622 uses three sets of power supply pins: an analog
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.3 V
and 5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply, as shown in Figure 24.
Power Sequencing
The AD7622 is independent of power supply sequencing and
thus free from supply induced voltage latch-up. In addition, it is
very insensitive to power supply variations over a wide
frequency range, as shown in Figure 30.
65.0
45.0
1
10000
FREQUENCY (kHz)
PSR
R
(
d
B)
10
100
1000
47.5
50.0
52.5
55.0
57.5
60.0
62.5
0
60
23-
02
9
EXT REF
INT REF
Figure 30. PSRR vs. Frequency
Power-Up
At power-up, or when returning to operational mode from the
power-down mode (PD = high), the AD7622 engages an
initialization process. During this time, the first 128 conversions
should be ignored or the RESET input could be pulsed to
engage a faster initialization process. Refer to the Digital
Interface section for RESET and timing details.
A simple power-on reset circuit, as shown in Figure 24, can be
used to minimize the digital interface. As OVDD powers up, the
capacitor is shorted and brings RESET high; it is then charged
returning RESET to low. However, this circuit only works when
powering up the AD7622 because the power-down mode
(PD = high) does not power down any of the supplies and as a
result, RESET is low.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, drive the digital inputs close to
the power rails (that is, OVDD and OGND).
CONVERSION CONTROL
The AD7622 is controlled by the CNVST input. A falling edge
on CNVST is all that is necessary to initiate a conversion.
Detailed timing diagrams of the conversion process are shown
in Figure 31. Once initiated, it cannot be restarted or aborted,
even by the power-down input, PD, until the conversion is
complete. The CNVST signal operates independently of CS and
RD signals.
BUSY
MODE
CONVERT
ACQUIRE
CONVERT
CNVST
t1
t2
t4
t3
t5
t6
t7
t8
06
02
3-
0
30
Figure 31. Basic Conversion Timing
For optimal performance, the rising edge of CNVST should not
occur after the maximum CNVST low time, t1, or until the end
of conversion.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
The CNVST trace should be shielded with ground and a low
value serial resistor (for example, 50 Ω) termination should be
added close to the output of the component that drives this line.
In addition, a 50 pF capacitor is recommended to further reduce
the effects of overshoot and undershoot as shown in Figure 24.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This can be achieved by using a dedicated
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 24.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7622BSTZ | 功能描述:IC ADC 16BIT DIFFERENTIAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7622BSTZRL | 功能描述:IC ADC 16BIT DIFFERENTL 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7623 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Power, Low Distortion |
| AD7623ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 1.33Msps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT, 2LSB, 1.33MSPS ADC - Bulk |
| AD7623ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.33Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
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