參數(shù)資料
型號(hào)： AD7631BCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/32頁(yè)
文件大小： 0K
描述： IC ADC 18BIT 250KSPS BIP 48LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 120mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
AD7631
Data Sheet
Rev. B | Page 24 of 32
INTERFACES
DIGITAL INTERFACE
The AD7631 has a versatile digital interface that can be set up as
either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The
AD7631 digital interface also accommodates 2.5 V, 3.3 V, or 5 V
logic. In most applications, the OVDD supply pin is connected
to the host system interface 2.5 V to 5.25 V digital supply. Finally,
by using the D0/OB/2C input pin, both twos complement or
straight binary coding can be used, except for a 18-bit parallel
interface.
Two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7631 in
multicircuit applications and is held low in a single AD7631
design. RD is generally used to enable the conversion result on
the data bus.
RESET
The RESET input is used to reset the AD7631. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7631 and clears
the data bus and configuration register. See Figure 36 for the
RESET timing details.
t9
t8
RESET
DATA
BUS
BUSY
CNVST
0
6
588
-03
6
Figure 36. RESET Timing
PARALLEL INTERFACE
The AD7631 is configured to use the parallel interface when the
MODE[1:0] pins = 0, 1, or 2 for 18-/16-/8-bit interfaces,
respectively, as shown in Table 7.
Master Parallel Interface
Data can be continuously read by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 37 details the timing for this mode.
t1
BUSY
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
CNVST
CS = RD = 0
t10
t4
t11
t3
0
6588
-037
Figure 37. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 38 and
Figure 39, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
CURRENT
CONVERSION
t13
t12
BUSY
DATA
BUS
RD
CS
06
58
8
-03
8
Figure 38. Slave Parallel Data Timing for Reading (Read After Convert)
PREVIOUS
CONVERSION
t13
t12
t3
BUSY
DATA
BUS
CNVST,
RD
CS = 0
t4
t1
06
58
8-
0
39
Figure 39. Slave Parallel Data Timing for Reading (Read During Convert)
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