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參數(shù)資料
| 型號： | AD7631BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 250KSPS BIP 48LFCSP |
| 標準包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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Data Sheet
AD7631
Rev. B | Page 17 of 32
THEORY OF OPERATION
SW+
COMP
SW–
IN+
REF
REFGND
LSB
MSB
131,072C
65,536C
4C
2C
C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
IN–
4C
2C
C
LSB
MSB
AGND
131,072C 65,536C
06
58
8
-02
5
Figure 25. ADC Simplified Schematic
OVERVIEW
The AD7631 is a very fast, low power, precise, 18-bit ADC
using successive approximation, capacitive digital-to-analog
(CDAC) architecture.
The AD7631 can be configured at any time for one of four input
ranges with inputs in parallel and serial hardware modes or by a
dedicated write-only, SPI-compatible interface via a configuration
register in serial software mode. The AD7631 uses Analog
Devices’ patented iCMOS high voltage process to accommodate
0 V to +5 V (10 V p-p), 0 V to +10 V (20 V p-p), ±5 V (20 V p-p),
and ±10 V (40 V p-p) input ranges on the fully differential IN+
and IN inputs without the use of conventional thin films. Only
one acquisition cycle, t8, is required for the inputs to latch to
the correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
The AD7631 is capable of converting 250,000 samples per
second (250 kSPS) and power consumption scales linearly with
throughput, making it useful for battery-powered systems.
The AD7631 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple, multiplexed channel
applications.
For unipolar input ranges, the AD7631 typically requires three
supplies: VCC, AVDD (which can supply DVDD), and OVDD
(which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic).
For bipolar input ranges, the AD7631 requires the use of the
additional VEE supply.
The device is housed in a Pb-free, 48-lead LQFP or a tiny,
48-lead, 7 mm × 7 mm LFCSP that combines space savings with
flexibility. In addition, the AD7631 can be configured as either a
parallel or serial SPI-compatible interface.
CONVERTER OPERATION
The AD7631 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 18 binary weighted capacitors, which are connected
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on IN+ and IN inputs. A
conversion phase is initiated once the acquisition phase is
complete and the CNVST input goes low. When the conversion
phase begins, SW+ and SW are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs (IN+ and IN) captured at the end of the acquisition
phase is applied to the comparator inputs, causing the comparator
to become unbalanced. By switching each element of the
capacitor array between REFGND and REF, the comparator
input varies by binary weighted voltage steps (VREF/2, VREF/4
through VREF/262,144). The control logic toggles these switches,
starting with the MSB first, to bring the comparator back into a
balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
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