- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10087 > AD7631BSTZRL (Analog Devices Inc)IC ADC 18BIT 250KSPS BIP 48-LQFP PDF資料下載
參數(shù)資料
| 型號： | AD7631BSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 250KSPS BIP 48-LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Data Sheet
AD7631
Rev. B | Page 29 of 32
HARDWARE CONFIGURATION
The AD7631 can be configured at any time with the dedicated
hardware pins BIPOLAR, TEN, D0/OB/2C, and PD for parallel
mode (MODE[1:0] = 0, 1, or 2) or serial hardware mode
(MODE[1:0] = 3, HW/SW = high). Programming the AD7631
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle, as indicated in
Figure 46. See Table 6 for pin descriptions. Note that these
inputs are high impedance when using the software
configuration mode.
SOFTWARE CONFIGURATION
The pins multiplexed on D[17:14] used for software
configuration are: HW/SW, SCIN, SCCLK, and SCCS. The
AD7631 is programmed using the dedicated write-only
serial configurable port (SCP) for conversion mode, input range
selection, output coding, and power-down using the serial
configuration register. See Table 11 for details of each bit in the
configuration register. The SCP can only be used in serial software
mode selected with MODE[1:0] = 3 and HW/SW = low because
the port is multiplexed on the parallel interface.
The SCP is accessed by asserting the port’s chip select, SCCS,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 47 for timing details. SCIN is clocked into the
configuration register MSB first. The configuration register is
an internal shift register that begins with Bit 8, the START bit.
The 9th SCCLK edge updates the register and allows the new
settings to be used. As indicated in the timing diagram, at least one
acquisition time is required from the 9th SCCLK edge. Bits [1:0] are
reserved bits and are not written to while the SCP is being updated.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7631 is not busy
converting, as detailed in Figure 47. In this mode, the full
670 kSPS is not attainable because the time required for SCP
access is (t31 + 9 × 1/SCCLK + t8) minimum. If the full
throughput is required, the SCP can be written to during
conversion; however, it is not recommended to write to the SCP
during the last 600 ns of conversion (BUSY = high) or performance
degradation can result. In addition, the SCP can be accessed in
both serial master and serial slave read during and read after
convert modes.
Note that at power-up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), therefore placing the configuration to 0 V to 5 V input,
normal mode, and twos complemented output.
Table 11. Configuration Register Description
Bit
Mnemonic
Description
8
START
START bit. With the SCP enabled (SCCS = low),
when START is high, the first rising edge of
SCCLK (INVSCLK = low) begins to load the
register with the new configuration.
7
BIPOLAR
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following.
Input Range (V)
BIPOLAR
TEN
0 to 5
Low
0 to 10
Low
High
±5
High
Low
±10
High
6
TEN
Input Range Select. See Bit 7, BIPOLAR.
5
PD
Power Down.
PD = low, normal operation.
PD = high, power down the ADC. The SCP is
accessible while in power down. To power up
the ADC, write PD = low on the next
configuration setting.
4
RSV
Reserved.
3
RSV
Reserved.
2
OB/2C
Output coding.
OB/2C = low, use twos complement output.
OB/2C = high, use straight binary output.
1
RSV
Reserved.
0
RSV
Reserved.
D0/OB/2C,
PD
BUSY
HW/SW = 1
CNVST
BIPOLAR,
TEN
t8
PD = 0
t8
0
65
88
-0
46
Figure 46. Hardware Configuration Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B3P-IV-F2 | CONVERTER MOD DC/DC 13.8V 150W |
| VE-B6L-MW-F1 | CONVERTER MOD DC/DC 28V 100W |
| VI-B3P-IV-F1 | CONVERTER MOD DC/DC 13.8V 150W |
| VI-BTY-MX | CONVERTER MOD DC/DC 3.3V 49.5W |
| VI-B3N-IV-F4 | CONVERTER MOD DC/DC 18.5V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7634 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
| AD7634BCPZ | 功能描述:IC ADC 18BIT BIPO PROGR 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7634BCPZRL | 功能描述:IC ADC 18BIT DIFF BIPO 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7634BSTZ | 功能描述:IC ADC 18BIT DIFF BIPO 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7634BSTZRL | 功能描述:IC ADC 18BIT DIFF BIPO 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復。