AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = 15 V; V
參數(shù)資料
型號(hào): AD7631BSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 28/32頁
文件大?。?/td> 0K
描述: IC ADC 18BIT 250KSPS BIP 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: PulSAR®
位數(shù): 18
采樣率(每秒): 250k
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 120mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
Data Sheet
AD7631
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = 15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION AND RESET (See Figure 35 and Figure 36)
Convert Pulse Width
t1
10
ns
Time Between Conversions
t2
4.0
μs
CNVST Low to BUSY High Delay
t3
35
ns
BUSY High All Modes (Except Master Serial Read After Convert)
t4
1.68
μs
Aperture Delay
t5
2
ns
End of Conversion to BUSY Low Delay
t6
10
ns
Conversion Time
t7
1.68
μs
Acquisition Time
t8
2.32
ns
RESET Pulse Width
t9
10
ns
PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)
CNVST Low to DATA Valid Delay
t10
1.65
μs
DATA Valid to BUSY Low Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
2
15
ns
MASTER SERIAL INTERFACE MODES1 (See Figure 41 and Figure 42)
CS Low to SYNC Valid Delay
t14
10
ns
CS Low to Internal SDCLK Valid Delay1
t15
10
ns
CS Low to SDOUT Delay
t16
10
ns
CNVST Low to SYNC Delay, Read During Convert
t17
530
ns
SYNC Asserted to SDCLK First Edge Delay
t18
3
ns
Internal SDCLK Period2
t19
30
45
ns
Internal SDCLK High2
t20
15
ns
Internal SDCLK Low2
t21
10
ns
SDOUT Valid Setup Time2
t22
4
ns
SDOUT Valid Hold Time2
t23
5
ns
SDCLK Last Edge to SYNC Delay2
t24
5
ns
CS High to SYNC HIGH-Z
t25
10
ns
CS High to Internal SDCLK HIGH-Z
t26
10
ns
CS High to SDOUT HIGH-Z
t27
10
ns
BUSY High in Master Serial Read After Convert2
t28
CNVST Low to SYNC Delay, Read After Convert
t29
1.5
μs
SYNC Deasserted to BUSY Low Delay
t30
25
ns
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1
External SDCLK, SCCLK Setup Time
t31
5
ns
External SDCLK Active Edge to SDOUT Delay
t32
2
18
ns
SDIN/SCIN Setup Time
t33
5
ns
SDIN/SCIN Hold Time
t34
5
ns
External SDCLK/SCCLK Period
t35
25
ns
External SDCLK/SCCLK High
t36
10
ns
External SDCLK/SCCLK Low
t37
10
ns
1 In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
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