參數(shù)資料
型號(hào)： AD7641ACPRL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48
封裝： MO-220-VKKD, LFCSP-48
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 324K
代理商： AD7641ACPRL
AD7641
Preliminary Technical Data
CONVERTER OPERATION
The AD7641 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 5 shows
the simplified schematic of the ADC. The capacitive DAC
consists of two identical arrays of 18 binary weighted capacitors
which are connected to the two comparator inputs.
Rev. Pr E | Page 12 of 24
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW-.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN- inputs. When the
acquisition phase is complete and the CNVST input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW- are opened first. The two capacitor arrays
are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
inputs IN+ and IN- captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND or REF, the comparator input varies by
binary weighted voltage steps (V
REF
/2, V
REF
/4 . . . V
REF
/262144).
The control logic toggles these switches, starting with the MSB
first, in order to bring the comparator back into a balanced
condition. After the completion of this process, the control logic
generates the ADC output code and brings BUSY output low.
MODES OF OPERATION
The AD7641 features two modes of operations; Warp and
Normal. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 2 MSPS.
However, in this mode, and this mode only, the full specified
accuracy is guaranteed only when the time between conversion
does not exceed 1 ms. If the time between two consecutive
conversions is longer than 1 ms, for instance, after power-up, the
first conversion result should be ignored. This mode makes the
AD7641 ideal for applications where fast sample rate are
required.
The normal mode is the fastest mode (1.5 MSPS) without any
limitation about the time between conversions. This mode
makes the AD7641 ideal for asynchronous applications such as
data acquisition systems, where both high accuracy and fast
sample rate are required.
TRANSFER FUNCTIONS
Except in 18 Bit interface mode, using the OB/2C digital input,
the AD7641 offers two output codings: straight binary and two’s
complement. The ideal transfer characteristic for the AD7641 is
shown in Figure 6 and Table 7.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS-1.5 LSB
+FS-1 LSB
-FS+1 LSB
-FS
-FS+0.5 LSB
Figure 6. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Digital Output Code (Hex)
Analog Input
V
REF
= 2.048V
Binary
2.047984 V
3FFFF
1
2.047969 V
3FFFE
15.625μV
20001
0 V
20000
-15.625μV
1FFFF
-2.047984 V
00001
-2.048 V
00000
2
Description
FSR –1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
-FSR + 1 LSB
-FSR
Straight
Twos
Complement
1FFFF
1
1FFE
00001
00000
3FFFF
20001
20000
2
1
This is also the code for overrange analog input (V
IN+
– V
IN-
above V
REF
–
V
REFGND
).
2
This is also the code for underrange analog input (V
IN+
– VI
N-
below -V
REF
+
V
REFGND
).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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