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參數(shù)資料
| 型號： | AD7650ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT CMOS 5V 48LQFP |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 570k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 77mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | EVAL-AD7650CBZ-ND - BOARD EVALUATION FOR AD7650 |
REV. 0
–7–
AD7650
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Type
Description
16
DATA[7]
DI/O
When SER/
PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT. When EXT/INT is
HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from
two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on
DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be
output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground
21
DATA[8]
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7650
provides the conversion result, MSB first, from its internal shift register. The DATA format
is determined by the logic level of OB/2C. In serial mode, when EXT/
INT is LOW, SDOUT
is valid on both edges of SCLK.
In serial mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
22
DATA[9]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
DATA[10]
DO
When SER/
PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/
PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
24
DATA[11]
DO
When SER/
PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as a incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
DATA[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless
of the state of SER/
PAR.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
CS is also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7650. Current conversion if any is aborted.
If not used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
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