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參數(shù)資料
| 型號： | AD7651ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 709K |
| 代理商： | AD7651ASTRL |
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AD7651
POWER DISSIPATION VERSUS THROUGHPUT
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see
). The AD7651 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 ) termination should be added
close to the output of the component that drives this line.
Figure 25
Figure 25. Power Dissipation vs. Sampling Rate
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in
.
Figure 22
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
02964-0-011
CNVST
100000
P
μ
W
SAMPLING RATE (SPS)
100k
1k
10
100
10k
10000
1000
100
10
02964-0-038
PDREF = PDBUF = PDHIGH
CONVERSION CONTROL
Figure 26
shows the detailed timing diagrams of the conversion
process. The AD7651 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD.
Figure 26. Basic Conversion Timing
t
9
t
8
RESET
DATA
BUSY
02964-0-011
CNVST
Figure 27. RESET Timing
Conversions can be automatically initiated with the AD7651. If
CNVST is held LOW when BUSY is LOW, the AD7651 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST LOW, the AD7651 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7651 can run slightly
faster than the guaranteed 100 kSPS.
t
1
t
3
t
4
t
11
BUSY
DATA
BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA
NEW DATA
02964-0-012
CNVST
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
Rev. 0 | Page 19 of 28
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7651ASTZ | 功能描述:IC ADC 16BIT 100KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7651ASTZ | 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7651 LQFP48 |
| AD7651ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7652ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT 500KSPS SAR UNIPOLAR ADC W/ REF - Bulk 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7652 LFSCP-48 |
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