- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373911 > AD7651ASTRL (ANALOG DEVICES INC) 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7651ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 100 kSPS PulSAR Unipolar ADC with Reference |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 709K |
| 代理商： | AD7651ASTRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD7651
MASTER SERIAL INTERFACE
Internal Clock
The AD7651 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7651 also
generates a SYNC signal to indicate to the host when the serial data
is valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on the RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figure 32
and Figure 33 show detailed timing diagrams of these two modes.
Usually, because the AD7651 has a longer acquisition phase than
the conversion phase, the data is read immediately after conversion.
This makes the Master Read After Conversion the most recom-
mended serial mode when it can be used. In this mode, it should be
noted that unlike in other modes, the BUSY signal returns LOW
after the 16 data bits are pulsed out and not at the end of the
conversion phase, which results in a longer BUSY width.
In the Read During Conversion mode, the serial clock and data
toggle at appropriate instants, which minimize potential feed-
through between digital activity and critical conversion decisions
t
3
BUSY
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
02964-0-015
CNVST
CS, RD
EXT/INT = 0
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
BUSY
SYNC
SCLK
SDOUT
02964-0-016
CNVST
CS, RD
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
Rev. 0 | Page 21 of 28
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7654 | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| AD7654ACP | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| AD7654ACPRL | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| AD7654AST | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| AD7654ASTRL | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7651ASTZ | 功能描述:IC ADC 16BIT 100KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7651ASTZ | 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7651 LQFP48 |
| AD7651ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7652ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT 500KSPS SAR UNIPOLAR ADC W/ REF - Bulk 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7652 LFSCP-48 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。