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參數(shù)資料
| 型號： | AD7654ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual 2-Channel Simultaneous Sampling SAR 500 kSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 734K |
| 代理商： | AD7654ASTRL |
REV. 0
–4–
AD7654
TIMING SPECIFICATIONS
(continued)
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 15 and 16 (Master Serial Interface Modes)
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay (Read during Convert)
(Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
*
Internal SCLK Period
*
Internal SCLK HIGH
*
Internal SCLK LOW
*
SDOUT Valid Setup Time
*
SDOUT Valid Hold Time
*
SCLK Last Edge to SYNC Delay
*
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
(Normal Mode/Impulse Mode)
CNVST
LOW to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
21
t
22
t
23
10
10
10
ns
ns
ns
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
250/500
ns
ns
ns
ns
ns
ns
ns
3
23
12
7
4
2
1
40
10
10
10
ns
ns
ns
t
35
See Table I
t
36
t
37
0.75/1
25
μ
s
ns
Refer to Figures 17 and 18 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t
38
t
39
t
40
t
41
t
42
t
43
t
44
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
*
In Serial Master Read during Convert Mode. See Table I for Serial Master Read after Convert Mode.
Specifications subject to change without notice.
Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum (Normal)
Busy High Width Maximum (Impulse)
t
25
t
26
t
26
t
27
t
28
t
29
t
30
t
31
t
35
t
35
3
25
40
12
7
4
2
1
3.25
3.5
17
50
70
22
21
18
4
3
4.25
4.5
17
100
140
50
49
18
30
30
6.25
6.5
17
200
280
100
99
18
80
80
10.75
11
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
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