參數(shù)資料
型號(hào): AD7655AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Low Cost 4-Channel 1 MSPS 16-Bit ADC
中文描述: 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: SEPOSEDPAD, MS-026BBC, LQFP-48
文件頁數(shù): 14/20頁
文件大小: 684K
代理商: AD7655AST
REV. 0
–14–
AD7655
FREQUENCY – kHz
401
10
P
100
1000
10000
45
50
55
60
65
70
Figure 6. PSRR vs. Frequency
POWER DISSIPATION
In impulse mode, the AD7655 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 7. This feature makes the AD7655
ideal for very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
SAMPLING RATE – kSPS
0.1
1
10
P
100
1000
1
10
100
1000
NORMAL
IMPULSE
Figure 7. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 8 shows the detailed timing diagrams of the conversion
process. The AD7655 is controlled by the signal
CNVST
, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The
CNVST
signal operates independently of the
CS
and
RD
signals. The A0 signal is the MUX select signal that
chooses which input signal is to be sampled. When high, INx1 is
chosen and when low, INx2 is chosen, where x is either A or B.
It should be noted that this signal should not be changed during
the acquisition phase of the converter.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT A
ACQUIRE
CONVERT
CONVERT B
EOC
t
12
A0
t
14
t
15
t
13
t
11
t
10
Figure 8. Conversion Control
In impulse mode, conversions can be automatically initiated. If
CNVST
is held low when BUSY is low, the AD7655 controls
the acquisition phase and then automatically initiates a new
conversion. By keeping
CNVST
low, the AD7655 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST
should be brought low once to initiate the
conversion process. In this mode, the AD7655 could sometimes
run slightly faster than the guaranteed limits in the impulse
mode of 888 kSPS. This feature does not exist in normal mode.
Although
CNVST
is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the
CNVST
signal should
have a very low jitter. Some solutions to achieve this are to
use a
dedicated oscillator for
CNVST
generation or, at least, to clock
it with a high frequency low jitter clock, as shown in Figure 4.
t
9
RESET
DATA BUS
BUSY
CNVST
t
8
Figure 9. Reset Timing
DIGITAL INTERFACE
The AD7655 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7655 digital interface also accommodates either 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7655
to the host system interface digital supply.
相關(guān)PDF資料
PDF描述
AD7655ASTRL Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7660 Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4
AD7660AST 16-Bit, 100 kSPS CMOS ADC
AD7660ASTRL 16-Bit, 100 kSPS CMOS ADC
AD7664 Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4
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