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參數(shù)資料
| 型號： | AD7655AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Cost 4-Channel 1 MSPS 16-Bit ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | SEPOSEDPAD, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 684K |
| 代理商： | AD7655AST |
REV. 0
–6–
AD7655
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Type
Description
1, 47, 48
2
3
AGND
AVDD
A0
P
P
DI
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously,
then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then
converted.
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Data Channel Selection. In parallel mode, when LOW, the data from channel B is read.
When HIGH, the data from channel A is read. In serial mode, when HIGH, channel A is
output first followed by channel B. When LOW, channel B is output first followed by channel A.
Digital Power Ground Pin.
Mode Selection. When HIGH, this input selects a reduced power mode, IMPULSE. In this
mode, the power dissipation is approximately proportional to the sampling rate. When LOW,
the mode NORMAL is selected.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these outputs
are in high impedance.
When SER/
PAR
is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, EXT/
INT
is LOW and RDC/SDIN is LOW which is the serial master
read after convert mode, these inputs, part of the serial port, are used to slow down if desired the
internal serial clock which clocks the data output. In the other serial modes, these inputs are not used.
When SER/
PAR
is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock, called respectively, master and slave mode. With
EXT/
INT
tied LOW, the internal clock is selected on SCLK output. With EXT/
INT
set to a logic
HIGH, output data is synchronized to an external clock signal connected to the SCLK input.
When SER/
PAR
is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
4
BYTESWAP
DI
5
A/
B
DI
6, 20
7
DGND
IMPULSE
DI
8
SER/
PAR
DI
9, 10
D[0:1]
DO
11, 12
D[2:3] or
DI/O
DIVSCLK[0:1]
13
D[4]
or EXT/
INT
DI/O
14
D[5]
or INVSYNC
DI/O
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
DVDD
CNVST
PD
RESET
CS
RD
EOC
BUSY
D15
D14
D13
D12
AGND
AVDD
A0
BYTESWAP
A/
B
DGND
IMPULSE
SER/
PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
AD7655
A
A
I
I
I
R
R
I
I
I
R
R
D
I
D
D
D
O
O
D
D
D
D
D
D
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|---|---|
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