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參數(shù)資料
| 型號： | AD7660AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD7660AST |
REV. 0
AD7660
–11–
000...000
000...001
000...010
111...101
111...110
111...111
A
–
ANALOG INPUT
V
REF
–
1.5 LSB
V
REF
–
1 LSB
1 LSB
0V
0.5 LSB
1 LSB = V
REF
/65536
Figure 4. ADC Ideal Transfer Function
Transfer Functions
Using the OB/
2C
digital input, the AD7660 offers two output
codings: straight binary and two’s complement. The LSB size is
V
REF
/65536, which is about 38.15
μ
V. The ideal transfer charac-
teristic for the AD7660 is shown in Figure 4 and Table I.
Table I. Output Codes and Ideal Input Voltages
Digital Output Code
(Hexa)
Straight
Binary
FFFF
1
FFFE
8001
8000
7FFF
0001
0000
2
Analog
Input
Two’s
Complement
7FFF
1
7FFE
0001
0000
FFFF
8001
8000
2
Description
FSR – 1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
2.499962 V
2.499923 V
1.250038 V
1.25 V
1.249962 V
38
μ
V
0 V
NOTES
1
This is also the code for overrange analog input (V
IN
– V
INGND
above
V
REF
– V
REFGND
).
2
This is also the code for underrange analog input (V
IN
below V
INGND
).
CIRCUIT INFORMATION
The AD7660 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7660 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 21
μ
W. This feature
makes the AD7660 ideal for battery-powered applications.
The AD7660 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7660 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and allows
flexible configurations as either serial or parallel interface. The
AD7660 is pin-to-pin-compatible with the AD7664.
CONVERTER OPERATION
The AD7660 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected
to a “dummy” capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW
A
. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the
CNVST
input
goes or is low, a conversion phase is initiated. When the conver-
sion phase begins, SW
A
and SW
B
are opened first. The capacitor
array and the “dummy” capacitor are then disconnected from
the inputs and connected to the REFGND input. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs, caus-
ing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (V
REF
/2, V
REF
/4 . . . V
REF
/65536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the comple-
tion of this process, the control logic generates the ADC output
code and brings BUSY output low.
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
LSB
MSB
32768C
INGND
16384C
4C
2C
C
C
67536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
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