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參數(shù)資料
| 型號(hào)： | AD7660AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大小： | 218K |
| 代理商： | AD7660AST |
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REV. 0
AD7660
–5–
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
Description
1
2
3, 6, 7,
40–48
4
5
AGND
AVDD
NC
P
P
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
DGND
OB/
2C
DI
DI
Must be tied to digital ground.
Straight Binary/Binary Two’s Complement. When OB/
2C
is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless
of the state of SER/
PAR
.
When SER/
PAR
is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/
INT
tied LOW, the internal
clock is selected on SCLK output. With EXT/
INT
set to a logic HIGH, output data is syn-
chronized to an external clock signal connected to the SCLK input.
When SER/
PAR
is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
When SER/
PAR
is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT
.
When EXT/
INT
is HIGH, RDC/SDIN could be used as a data input to daisy chain the con-
version results from two or more ADCs onto a single SDOUT line. The digital data level on
SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data is output on SDOUT only when the conversion is complete.
Input/Output interface Digital Power Ground.
Input/Output interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground.
When SER/
PAR
is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C
. In serial mode, when EXT/
INT
is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
8
SER/
PAR
DI
9–12
DATA[0:3]
DO
13
DATA[4]
or EXT/
INT
DI/O
14
DATA[5]
or INVSYNC
DI/O
15
DATA[6]
or INVSCLK
DI/O
16
DATA[7]
or RDC/SDIN
DI/O
17
18
OGND
OVDD
P
P
19
20
21
DVDD
DGND
DATA[8]
or SDOUT
P
P
DO
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