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參數(shù)資料
| 型號： | AD7677ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DIFF INP 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 7 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 130mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7677CBZ-ND - BOARD EVALUATION FOR AD7677 |
REV. A
AD7677
–6–
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Type
Description
1
AGND
P
Analog Power Ground Pin
2
AVDD
P
Analog Power Pin. Nominally 5 V.
3,
NC
No Connect
40–42,
44–48
4
BYTESWAP
DI
Parallel Mode Selection (8-bit/16-bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is
output on D[7:0].
5OB/
2C
DI
Straight Binary/Binary Two’s Complement. When OB/
2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from
its internal shift register.
6
WARP
DI
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the
maximum throughput is achievable, and a minimum conversion rate must be applied in order to
guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the
minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
DATA[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these outputs
are in high impedance.
11, 12
DATA[2:3] or
DI/O
When SER/
PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1]
When SER/
PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial
master read after convert mode. These inputs, part of the serial port, are used to slow down if
desired the internal serial clock which clocks the data output. In the other serial modes, these
pins are high impedance outputs.
13
DATA[4]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
or EXT/
INT
When SER/
PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/
INT tied LOW, the internal clock
is selected on SCLK output. With EXT/
INT set to a logic HIGH, output data is synchro-
nized to an external clock signal connected to the SCLK input.
14
DATA[5]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15
DATA[6]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/
PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
16
DATA[7]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT. When EXT/INT is
HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from
two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on
DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output
on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
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| AD7677ACPZRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 16BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel |
| AD7677AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:57BKSPS 16-BIT 1LSB INL DIFFERENTIAL ADC - Tape and Reel 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7677ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7677ASTZ | 功能描述:IC ADC 16BIT 1MSPS DIFF 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7677ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
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