參數(shù)資料
    型號: AD7679ACPZRL
    廠商: Analog Devices Inc
    文件頁數(shù): 7/28頁
    文件大?。?/td> 0K
    描述: IC ADC 18BIT SAR W/BUFF 48LFCSP
    標準包裝: 2,500
    系列: PulSAR®
    位數(shù): 18
    采樣率(每秒): 570k
    數(shù)據(jù)接口: 串行,并聯(lián)
    轉(zhuǎn)換器數(shù)目: 1
    功率耗散(最大): 103mW
    電壓電源: 模擬和數(shù)字
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 48-VFQFN 裸露焊盤,CSP
    供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 1 個差分,雙極
    配用: EVAL-AD7679CBZ-ND - BOARD EVALUATION FOR AD7679
    AD7679
    Rev. A | Page 15 of 28
    CIRCUIT INFORMATION
    IN+
    REF
    REFGND
    IN–
    MSB
    4C
    2C
    C
    LSB
    SW+
    SWITCHES
    CONTROL
    262,144C 131,072C
    MSB
    4C
    2C
    C
    LSB
    SW–
    BUSY
    OUTPUT
    CODE
    CNVST
    CONTROL
    LOGIC
    COMP
    262,144C 131,072C
    03085–0–025
    Figure 23. ADC Simplified Schematic
    The AD7679 is a very fast, low power, single-supply, precise
    18-bit analog-to-digital converter (ADC) using successive
    approximation architecture.
    The AD7679’s linearity and dynamic range are similar or better
    than many Σ-Δ ADCs. With the advantages of its successive
    architecture, which ease multiplexing and reduce power with
    throughput, it can be advantageous in applications that
    normally use Σ-Δ ADCs.
    The AD7679 provides the user with an on-chip track/hold,
    successive approximation ADC that does not exhibit any
    pipeline or latency, making it ideal for multiple multiplexed
    channel applications.
    The AD7679 can be operated from a single 5 V supply and can
    be interfaced to either 5 V or 3 V digital logic. It is housed in a
    48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
    and allows for flexible configurations as either a serial or
    parallel interface. The AD7679 is pin-to-pin compatible with
    the AD7674, AD7676, and AD7678.
    CONVERTER OPERATION
    The AD7679 is a successive approximation ADC based on a
    charge redistribution DAC. Figure 23 shows the simplified
    schematic of the ADC. The capacitive DAC consists of two
    identical arrays of 18 binary weighted capacitors that are
    connected to the two comparator inputs.
    During the acquisition phase, terminals of the array tied to the
    comparator’s input are connected to AGND via SW+ and SW–.
    All independent switches are connected to the analog inputs.
    Thus, the capacitor arrays are used as sampling capacitors and
    acquire the analog signal on IN+ and IN– inputs. When the
    acquisition phase is complete and the CNVST input goes low, a
    conversion phase is initiated. When the conversion phase
    begins, SW+ and SW– are opened first. The two capacitor
    arrays are then disconnected from the inputs and connected to
    the REFGND input. Therefore, the differential voltage between
    the IN+ and IN– inputs captured at the end of the acquisition
    phase is applied to the comparator inputs, causing the
    comparator to become unbalanced. By switching each element
    of the capacitor array between REFGND and REF, the
    comparator input varies by binary weighted voltage steps
    (VREF/2, VREF/4...VREF/262144). The control logic toggles these
    switches, starting with the MSB first, to bring the comparator
    back into a balanced condition. After completing this process,
    the control logic generates the ADC output code and brings the
    BUSY output low.
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