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參數(shù)資料
| 型號： | AD7679ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT SAR W/BUFF 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 570k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 103mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7679CBZ-ND - BOARD EVALUATION FOR AD7679 |
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AD7679
Rev. A | Page 17 of 28
TYPICAL CONNECTION DIAGRAM
Figure 25 shows a typical connection diagram for the AD7679.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.
Analog Inputs
Figure 26 shows a simplified analog input section of the
AD7679. The diodes shown in Figure 26 provide ESD
protection for the inputs. Care must be taken to ensure that the
analog input signal never exceeds the absolute ratings on these
inputs. This will cause these diodes to become forward biased
and start conducting current. These diodes can handle a
forward-biased current of 120 mA max. This condition could
eventually occur when the input buffer’s U1 or U2 supplies are
different from AVDD. In such a case, an input buffer with a
short-circuit current limitation can be used to protect the part.
IN+
IN–
AGND
AVDD
R+ = 102
Ω
CS
R– = 102
Ω
03085-0-028
Figure 26. Simplified Analog Input
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 27, which represents typical
CMRR over frequency.
FREQUECY (kHz)
80
CMRR
(dB)
75
50
100
1000
10000
110
70
65
60
55
03085-0-029
Figure 27. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the AD7679
behaves like a 1-pole RC filter consisting of the equivalent
resistance, R+, R–, and CS. Resistors R+ and R– are typically
102 Ω and are lumped components made up of a serial resistor
and the on resistance of the switches. CS is typically 60 pF and
mainly consists of the ADC sampling capacitor. This 1-pole
filter with a –3 dB cutoff frequency of 26 MHz typ reduces any
undesirable aliasing effect and limits the noise coming from the
inputs.
Because the input impedance of the AD7679 is very high, the
part can be driven directly by a low impedance source without
gain error. This allows the user to put an external 1-pole RC
filter between the amplifier output and the ADC analog inputs,
as shown in Figure 25, to even further improve the noise
filtering done by the AD7679 analog input circuit. However, the
source impedance has to be kept low because it affects the ac
performance, especially the total harmonic distortion (THD).
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades as a function of
source impedance and the maximum input frequency, as shown
INPUT RESISTANCE (
Ω)
–95
THD
(dB)
–120
45
75
105
15
–100
–105
–110
–115
20kHz
10kHz
2kHz
03085-0-030
Figure 28. THD vs. Analog Input Frequency and Source Resistance
Driver Amplifier Choice
Although the AD7679 is easy to drive, the driver amplifier
needs to meet the following requirements:
The driver amplifier and the AD7679 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier’s data
sheet, settling at 0.1% or 0.01% is more commonly
specified. This could differ significantly from the settling
time at an 18-bit level and, therefore, should be verified
prior to driver selection. The tiny op amp AD8021, which
combines ultralow noise and high gain-bandwidth, meets
this settling time requirement.
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7679. The noise
coming from the driver is filtered by the AD7679 analog
input circuit 1-pole low-pass filter made by R+, R–, and CS.
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