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參數(shù)資料
| 型號： | AD7682BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 4CH 250KSPS 20LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring |
| 產(chǎn)品變化通告： | Startup Circuitry Design Improvement Change 15/April/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 21mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，雙極；4 個偽差分，雙極 |
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Data Sheet
AD7682/AD7689
Rev. D | Page 25 of 32
The register can be written to during conversion, during acquisi-
tion, or spanning acquisition/conversion, and is updated at the end
of conversion, tCONV (maximum). There is always a one deep
delay when writing the CFG register. Note that, at power-up, the
CFG register is undefined and two dummy conversions are
required to update the register. To preload the CFG register with a
factory setting, hold DIN high for two conversions. Thus
following:
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for a one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
Enables the internal sequencer
No readback of the CFG register
Table 10 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INx
BW
REF
SEQ
RB
Table 10. Configuration Register Description
Bit(s)
Name
Description
[13]
CFG
Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register.
[12:10]
INCC
Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer
to the
Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
Bipolar differential pairs; INx referenced to VREF/2 ± 0.1 V.
0
1
Bipolar; INx referenced to COM = VREF/2 ± 0.1 V.
0
1
Temperature sensor.
1
0
Unipolar differential pairs; INx referenced to GND ± 0.1 V.
1
0
Unipolar, INx referenced to COM = GND ± 0.1 V.
1
Unipolar, INx referenced to GND.
[9:7]
INx
Input channel selection in binary fashion.
Bit 9
Bit 8
Bit 7
Channel
Bit 9
Bit 8
Bit 7
Channel
0
IN0
0
IN0
0
1
IN1
0
1
IN1
1
0
IN2
…
1
IN3
1
IN7
[6]
BW
Select bandwidth for low-pass filter. Refer to the
Selectable Low-Pass Filter section.
0 = of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to .
1 = full BW.
[5:3]
REF
Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the
Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
Internal reference, REF = 2.5 V output,
temperature enabled.
0
1
Internal reference, REF = 4.096 V output,
temperature enabled.
0
1
0
External reference, temperature enabled.
0
1
External reference, internal buffer, temperature enabled.
1
0
External reference, temperature disabled.
1
External reference, internal buffer, temperature disabled.
[2:1]
SEQ
Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the
Channel Sequencer section.
Bit 2
Bit 1
Function
0
Disable sequencer.
0
1
Update configuration during sequence.
1
0
Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.
1
Scan IN0 to IN[7:0] (set in CFG[9:7]).
[0]
RB
Read back the CFG register.
0 = read back current configuration at end of data.
1 = do not read back contents of configuration.
1 X = don’t care.
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