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參數(shù)資料
型號: AD7682BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 6/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 4CH 250KSPS 20LFCSP
產(chǎn)品培訓模塊: Power Line Monitoring
產(chǎn)品變化通告: Startup Circuitry Design Improvement Change 15/April/2009
標準包裝: 1,500
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 250k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 21mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應商設備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;4 個差分,雙極;4 個偽差分,雙極
AD7682/AD7689
Data Sheet
Rev. D | Page 14 of 32
–60
–70
–80
–90
–100
–110
–120
0
50
100
150
200
T
HD
(
d
B)
FREQUENCY (kHz)
VREF = VDD = 5V, –0.5dB
VREF = VDD = 2.5V, –0.5dB
VREF = VDD = 2.5V, –10dB
VREF = VDD = 5V, –10dB
07
35
3-
0
15
Figure 18. THD vs. Frequency
95
94
93
92
91
90
89
88
87
86
85
–10
S
N
R
(
d
B)
INPUT LEVEL (dB)
–8
–6
–2
0
–4
fIN = 20kHz
VREF = VDD = 5V
VREF = VDD = 2.5V
07
35
3-
0
1
8
Figure 19. SNR vs. Input Level
3
2
1
0
–1
–2
–3
O
F
S
E
T
E
RRO
R
AN
D
G
A
IN
E
RRO
R
(
L
S
B)
–55
TEMPERATURE (°C)
–35
–15
5
25
45
65
85
105
125
UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
07
35
3-
0
20
Figure 20. Offset and Gain Errors vs. Temperature
3000
2750
2500
2250
2000
1750
1500
1250
1000
100
90
80
70
60
50
40
30
20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD
CUR
RE
NT
(
A)
V
IO
CUR
RE
NT
(
A)
VDD SUPPLY (V)
2.5V INTERNAL REF
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
VIO
fS = 200kSPS
07
35
3-
0
21
Figure 21. Operating Currents vs. Supply
3000
2750
2500
2250
2000
1750
1500
1250
1000
180
160
140
120
100
80
60
40
20
V
DD
CUR
RE
NT
(
A)
V
IO
CURR
E
NT
(
A)
–55
TEMPERATURE (°C)
–35
–15
5
25
45
65
85
105
125
fS = 200kSPS
VDD = 5V, INTERNAL 4.096V REF
VDD = 5V, EXTERNAL REF
VDD = 2.5, EXTERNAL REF
VIO
0
735
3-
0
22
Figure 22. Operating Currents vs. Temperature
07
35
3
-02
3
SDO CAPACITIVE LOAD (pF)
120
0
204060
80
100
t DS
D
O
DE
L
A
Y
(
n
s)
25
20
15
10
5
0
VDD = 2.5V, 85°C
VDD = 3.3V, 25°C
VDD = 3.3V, 85°C
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD = 2.5V, 25°C
Figure 23. tDSDO Delay vs. SDO Capacitance Load and Supply
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