參數(shù)資料
型號(hào)： AD7688BRMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/28頁(yè)
文件大小： 0K
描述： IC ADC DIFF 16BIT 500KSPS 10MSOP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
AD7688
Rev. A | Page 15 of 28
DRIVER AMPLIFIER CHOICE
Although the AD7688 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7688. Note that the
AD7688 has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system perform-
ance. The noise coming from the driver is filtered by the
AD7688 analog input circuit 1-pole, low-pass filter made
by RIN and CIN or by the external filter, if one is used.
Because the typical noise of the AD7688 is 53 μV rms,
the SNR degradation due to the amplifier is
+
=
2
)
(
2
π
5
53
20log
N
3dB
LOSS
Ne
f
SNR
3
where:
f–3dB is the input bandwidth in MHz of the AD7688
(9 MHz) or the cutoff frequency of the input filter, if one
is used.
N is the noise gain of the amplifier (for example, +1 in
buffer configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
For ac applications, the driver should have a THD
performance commensurate with the AD7688. Figure 18
shows the THD vs. frequency that the driver should
exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7688 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier
Typical Application
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power and low frequency
High frequency and low power
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, a single-ended-to-differential driver
allows for a differential input into the part. The schematic is
shown in Figure 30. When provided a single-ended input signal,
this configuration produces a differential ±VREF with midscale
at VREF/2.
U2
10k
Ω
590
Ω
AD7688
IN+
IN–
REF
U1
ANALOG INPUT
(
±10V, ±5V, ..)
590
Ω
10
μF
100nF
10k
Ω
VREF
590
Ω
100nF
VREF
02973-029
Figure 30. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7688 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8605, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7688 is specified at 4.5 V to 5.5 V. It has, unlike other
low voltage converters, a low enough noise to design a 16-bit
resolution system with low supply and respectable performance.
It uses two power supply pins: a core supply VDD and a digital
input/output interface supply VIO. VIO allows direct interface
with any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together. The AD7688 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 31,
which represents PSRR over frequency.
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