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參數(shù)資料
| 型號： | AD7691BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT SAR 250KSPS 10LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7691CBZ-ND - BOARD EVALUATION FOR AD7691CBZ |
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Data Sheet
AD7691
Rev. C | Page 19 of 28
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7691 then
enters the acquisition phase and powers down. The data bits
are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or when CNV goes high, whichever occurs first, SDO returns to
high impedance.
If multiple AD7691s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
47k
CNV
SCK
SDO
SDI
VIO
AD7691
06
14
6-
0
13
Figure 37. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
SDO
D17
D16
D1
D0
tDIS
SCK
123
17
18
19
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
06
14
6-
0
14
Figure 38. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
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