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參數(shù)資料
| 型號(hào)： | AD7703ARZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT LC2MOS 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 4k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 37mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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REV. E
–10–
AD7703
Initiating Calibration
Table III illustrates the calibration modes available in the AD7703.
Not shown in the table is the function of the BP/
UP pin, which
determines whether the converter has been calibrated to mea-
sure bipolar or unipolar signals. A calibration step is initiated by
bringing the CAL pin high for at least four CLKIN cycles and
then bringing it low again. The states of SC1 and SC2 along
with the BP/
UP pin will determine the type of calibration to be
performed. All three signals should be stable before the CAL
pin is taken positive. The SC1 and SC2 inputs are latched when
CAL goes high. The BP/
UP input is not latched and, therefore,
must remain in a fixed state throughout the calibration and
measurement cycles. Any time the state of the BP/
UP is changed,
a new calibration cycle must be performed to enable the AD7703
to function properly in the new mode.
When a calibration step is initiated, the
DRDY signal will go high
and remain high until the step is finished. Table III shows the
number of clock cycles each calibration requires. Once a calibra-
tion step is initiated, it must finish before a new calibration step
can be executed. In the two step system calibration mode, the
offset calibration step must be initiated before initiating the gain
calibration step.
When self-calibration is completed,
DRDY falls and the output
port is updated with a data-word that represents the analog input
signal. When a system calibration step is completed,
DRDY will
fall and the output port will be updated with the appropriate data
value (all 0s for the zero-scale point and all 1s for the full-scale
point). In the system calibration mode, the digital filter must
settle before the output code will represent the value of the
analog input signal. Tables IV and V indicate the output code
size and output coding of the AD7703 in its various modes. In
these tables, SOFF is the measured system offset in volts and
SGAIN is the measured system gain at the full-scale point in volts.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits
on the amount of offset and span that can be accommodated.
The range of input span in both the Unipolar and Bipolar
modes has a minimum value of 0.8 VREF and a maximum
value of 2(VREF + 0.1 V).
The amount of offset that can be accommodated depends on
whether the Unipolar or Bipolar mode is being used. In Unipolar
mode, the system calibration modes can handle a maximum
offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V).
Therefore the AD7703 in the Unipolar mode can be calibrated
to mimic bipolar operation.
Table III. Calibration Truth Table
*
Calibration
Zero-Scale
Full-Scale
Calibration
CAL
SC1
SC2
Type
Calibration
Sequence
Time
00
Self-Calibration
VAGND
VREF
One Step
3,145,655 Clock Cycles
11
System Offset
AIN
First Step
1,052,599 Clock Cycles
01
System Gain
AIN
Second Step
1,068,813 Clock Cycles
10
System Offset
AIN
VREF
One Step
2,117,389 Clock Cycles
*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other
modes,
DRDY falls as the device begins to settle.
Table IV. Output Code Size After Calibration
1 LSB
Calibration Mode
Zero Scale
Gain Factor
Unipolar
Bipolar
Self-Calibration
VAGND
VREF
(VREF –VAGND )
1048576
2(VREF –VAGND )
1048576
System Calibration
SOFF
SGAIN
(SGAIN – SOFF )
1048576
2(SGAIN – SOFF )
1048576
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