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參數(shù)資料
| 型號： | AD7706BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 3CH 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個偽差分，單極; 3 個偽差分，雙極 |
| 配用： | EVAL-AD7706EBZ-ND - BOARD EVALUATION FOR AD7706 |
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AD7705/AD7706
Rev. C | Page 24 of 44
Filter Characteristics
The AD7705/AD7706 digital filter is a low-pass filter with a
(sinx/x)3 response (also called sinc3). The transfer function for
the filter is described in the z-domain by
3
1
)
(
×
Z
N
z
H
N
and in the frequency domain by
()
3
/
sin
/
sin
1
)
(
S
f
N
f
H
×
π
×
π
×
=
where N is the ratio of the modulator rate to the output rate.
The phase response is defined by the following equation:
(
)
Rad
f
N
H
S
×
π
=
∠
2
3
Figure 15 shows the filter frequency response for a cutoff
frequency of 15.72 Hz, which corresponds to a first filter notch
frequency of 60 Hz. The plot is shown from dc to 390 Hz. This
response is repeated at either side of the digital filter’s sample
frequency and at either side of multiples of the filter’s sample
frequency.
The response of the filter is similar to that of an averaging filter,
but with a sharper roll-off. The output rate for the digital filter
corresponds with the positioning of the first notch of the filter’s
frequency response. Thus, for Figure 15, where the output rate
is 60 Hz, the first notch of the filter is at 60 Hz. The notches of
this (sinx/x)3 filter are repeated at multiples of the first notch.
The filter provides attenuation of better than 100 dB at these
notches.
The cutoff frequency of the digital filter is determined by the value
loaded to Bit FS0 and Bit FS1 in the clock register. Programming a
different cutoff frequency via Bit FS0 and Bit FS1 does not alter
the profile of the filter response, but changes the frequency of
the notches. The output update of the part and the frequency of
the first notch correspond.
Because the AD7705/AD7706 contain this on-chip, low-pass
filtering, a settling time is associated with step function inputs,
and data on the output is invalid after a step change until the
settling time has elapsed. The settling time depends on the output
rate chosen for the filter. The settling time of the filter to a full-
scale step input can be up to four times the output data period.
For a synchronized step input using the FSYNC function, the
settling time is three times the output data period.
FREQUENCY (Hz)
0
–140
–240
0
GAIN
(
d
B)
60
120
180
240
300
360
–20
–160
–180
–60
–100
–40
–80
–200
–220
–120
01166-015
Figure 15. Frequency Response of AD7705 Filter
Postfiltering
The on-chip modulator provides samples at a 19.2 kHz output rate
with fCLKIN at 2.4576 MHz. The on-chip digital filter decimates
these samples to provide data at an output rate that corresponds
to the programmed output rate of the filter. Because the output
data rate is higher than the Nyquist criterion, the output rate for
a given bandwidth satisfies most application requirements. Some
applications, however, might require a higher data rate for a
given bandwidth and noise performance. Applications that need
this higher data rate will require postfiltering following the digital
filtering performed by the AD7705/AD7706.
For example, if the required bandwidth is 7.86 Hz, but the
required update rate is 100 Hz, data can be taken from the
AD7705/AD7706 at the 100 Hz rate, giving a 3 dB bandwidth
of 26.2 Hz. Postfiltering can then be applied to reduce the
bandwidth and output noise to the 7.86 Hz bandwidth level
while maintaining an output rate of 100 Hz.
Postfiltering can also be used to reduce the output noise from
the devices for bandwidths below 13.1 Hz. At a gain of 128 and
a bandwidth of 13.1 Hz, the output rms noise is 450 nV. This is
essentially device noise, or white noise. Because the input is
chopped, the noise has a primarily flat frequency response. By
reducing the bandwidth below 13.1 Hz, the noise in the resultant
pass band is reduced. A reduction in bandwidth by a factor of 2
results in a reduction of approximately 1.25 in the output rms
noise. This additional filtering results in a longer settling time.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7706BRU-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 16TSSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:LOW COST 3CHNL 16-6 SIGMA DELTA ADC I.C. - Tape and Reel |
| AD7706BRU-REEL7 | 功能描述:IC ADC 16BIT 3CH 16-TSSOP T/R RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7706BRUZ | 功能描述:IC ADC 16BIT 3CH 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7706BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
| AD7706BRUZ-REEL | 功能描述:IC ADC 16BIT 3CHAN 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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