參數(shù)資料
型號(hào)： AD7706BRU
廠商： Analog Devices Inc
文件頁數(shù)： 9/44頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 16-TSSOP
標(biāo)準(zhǔn)包裝： 96
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)偽差分，單極; 3 個(gè)偽差分，雙極
配用： EVAL-AD7706EBZ-ND - BOARD EVALUATION FOR AD7706
AD7705/AD7706
Rev. C | Page 17 of 44
Table 11. Register Selection
RS2
RS1
RS0
Register
Register Size
0
Communication register
8 bits
0
1
Setup register
8 bits
0
1
0
Clock register
8 bits
0
1
Data register
16 bits
1
0
Test register
8 bits
1
0
1
No operation
1
0
Offset register
24 bits
1
Gain register
24 bits
Table 12. Channel Selection for AD7705
CH1
CH0
AIN(+)
AIN()
Calibration Register Pair
0
AIN1(+)
AIN1()
Register Pair 0
0
1
AIN2(+)
AIN2()
Register Pair 1
1
0
AIN1()
Register Pair 0
1
AIN1()
AIN2()
Register Pair 2
Table 13. Channel Selection for AD7706
CH1
CH0
AIN
Reference
Calibration Register Pair
0
AIN1
COMMON
Register Pair 0
0
1
AIN2
COMMON
Register Pair 1
1
0
COMMON
Register Pair 0
1
AIN3
COMMON
Register Pair 2
SETUP REGISTER (RS2, RS1, RS0 = 0, 0, 1); POWER-ON/RESET STATUS: 01 HEXADECIMAL
The setup register is an 8-bit register from which data can be read or to which data can be written.
Table 14 outlines the bit designations for the setup register.
Table 14. Setup Register
MD1 (0)
MD0 (0)
G2 (0)
G1 (0)
G0 (0)
B/U (0)
BUF (0)
FSYNC (1)
Table 15. Setup Register Description
Register
Description
MD1, MD0
ADC Mode Bits. These bits select the operational mode of the ADC as outlined in Table 16.
G2 to G0
Gain Selection Bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 17.
B/U
Bipolar/Unipolar Operation. A 0 in this bit selects bipolar operation; a 1 in this bit selects unipolar operation.
BUF
Buffer Control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current
flowing in the VDD line is reduced. When this bit is high, the on-chip buffer is in series with the analog input, allowing the input
to handle higher source impedances.
FSYNC
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, the calibration control logic,
and the analog modulator are held in a reset state. When this bit goes low, the modulator and filter start to process data, and
a valid word is available in 3 × 1/output rate, that is, the settling time of the filter. This FSYNC bit does not affect the digital
interface and does not reset the DRDY output if it is low.
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