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| 型號： | AD7711AR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 80°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
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REV. G
–20–
AD7711
Self-Clocking Mode
The AD7711 is configured for its self-clocking mode by tying
the MODE pin high. In this mode, the AD7711 provides the
serial clock signal used for the transfer of data to and from the
AD7711. This self-clocking mode can be used with processors
that allow an external device to clock their serial port, including
most digital signal processors and microcontrollers such as the
68HC11 and 68HC05. It also allows easy interfacing to serial-
parallel conversion circuits in systems with parallel data commu-
nication, allowing interfacing to 74XX299 universal shift
registers without any additional decoding. In the case of shift
registers, the serial clock line should have a pull-down resistor
instead of the pull-up resistor shown in Figures 10 and 11.
Read Operation
Data can be read from either the output register, the control
register, or the calibration registers. A0 determines whether the
data read accesses data from the control register or from the
output/calibration registers. This A0 signal must remain valid
for the duration of the serial read operation. With A0 high, data
is accessed from either the output register or the calibration
registers. With A0 low, data is accessed from the control register.
The function of the
DRDY line is dependent only on the output
update rate of the device and the reading of the output data
register.
DRDY goes low when a new data-word is available in
the output data register. It is reset high when the last bit of data
(either 16th bit or 24th bit) is read from the output register. If
data is not read from the output register, the
DRDY line re-
mains low. The output register continues to be updated at the
output update rate but
DRDY will not indicate this. A read
from the device in this circumstance accesses the most recent
word in the output register. If a new data-word becomes available
to the output register while data is being read from the output
register,
DRDY will not indicate this and the new data-word
will be lost to the user.
DRDY is not affected by reading from
the control register or the calibration registers.
t3
t5
t9
t8
t6
t4
t2
t7
t10
MSB
LSB
THREE-STATE
SDATA (O)
SCLK (O)
RFS (I)
A0 (I)
DRDY (O)
Figure 10. Self-Clocking Mode, Output Data Read Operation
Data can be accessed from the output data register only when
DRDY is low. If RFS goes low with DRDY high, no data trans-
fer takes place.
DRDY does not have any effect on reading data
from the control register or from the calibration registers.
Figure 10 shows a timing diagram for reading from the AD7711
in the self-clocking mode. The read operation shows a read from
the AD7711’s output data register. A read from the control
register or calibration registers is similar, but, in these cases, the
DRDY line is not related to the read function. Depending on
the output update rate, it can go low at any stage in the control/
calibration register read cycle without affecting the read, and its
status should be ignored. A read operation from either the con-
trol or calibration registers must always read 24 bits of data
from the respective register.
Figure 10 shows a read operation from the AD7711. For the
timing diagram shown, it is assumed that there is a pull-up
resistor on the SCLK output. With
DRDY low, the RFS
input is brought low.
RFS going low enables the serial clock of
the AD7711 and also places the MSB of the word on the serial
data line. All subsequent data bits are clocked out on a high to
low transition of the serial clock and are valid prior to the follow-
ing rising edge of this clock. The final active falling edge of
SCLK clocks out the LSB, and this LSB is valid prior to the final
active rising edge of SCLK. Coincident with the next falling
edge of SCLK,
DRDY is reset high. DRDY going high turns off
the SCLK and the SDATA outputs, which means the data hold
time for the LSB is slightly shorter than for all other bits.
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| AD7711AR-REEL7 | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7711ARZ | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7711ARZ | 制造商:Analog Devices 功能描述:LC 2MOS SIGNAL CONDITIONING ANALOG/DIGIT |
| AD7711ARZ-REEL | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7711ARZ-REEL7 | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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