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參數(shù)資料
| 型號(hào)： | AD7711AR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT RTD I SOURCE 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 1.03k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 52.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 80°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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2
REV.G
AD7711
–23–
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY line and does not have any effect on the status of
DRDY. A write operation to the control register or the calibra-
tion register must always write 24 bits.
Figure 13a shows a write operation to the AD7711 with
TFS
remaining low for the duration of the operation. A0 determines
whether a write operation transfers data to the control register
or to the calibration registers. This A0 signal must remain valid
for the duration of the serial write operation. As before, the serial
clock line should be low between read and write operations. The
serial data to be loaded to the AD7711 must be valid on the
high level of the externally applied SCLK signal. Data is clocked
into the AD7711 on the high level of this SCLK signal with the
MSB transferred first. On the last active high time of SCLK, the
LSB is loaded to the AD7711.
Figure 13b shows a timing diagram for a write operation to the
AD7711 with
TFS returning high during the operation and
returning low again to write the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when
TFS returns high in the middle
of transferring a word.
Data to be loaded to the AD7711 must be valid prior to the
rising edge of the SCLK signal.
TFS should return high during
the low time of SCLK. After
TFS returns low again, the next bit
of the data-word to be loaded to the AD7711 is clocked in on
next high level of the SCLK input. On the last active high time
of the SCLK input, the LSB is loaded to the AD7711.
t32
t35
t36
t27
t26
t33
t34
MSB
LSB
SDATA (I)
SCLK (I)
TFS (I)
A0 (I)
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
SDATA (I)
SCLK (I)
TFS (I)
A0 (I)
t32
t26
t30
t35
t36
t27
MSB
BIT N
BIT N+1
t35
t36
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation
(
TFS Returns High during Write Operation)
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