參數(shù)資料
型號(hào)： AD7711AR
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT RTD I SOURCE 24SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 1.03k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 52.5mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 80°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
REV. G
–22–
AD7711
Figures 12a and 12b show timing diagrams for reading from the
AD7711 in external clocking mode. In Figure 12a, all the data is
read from the AD7711 in one operation. In Figure 12b, the data
is read from the AD7711 over a number of read operations. Both
read operations show a read from the AD7711’s output data
register. A read from the control register or calibration registers is
similar, but, in these cases, the
DRDY line is not related to the
read function. Depending on the output update rate, it can go
low at any stage in the control/calibration register read cycle
without affecting the read, and its status should be ignored. A
read operation from either the control or calibration registers
must always read 24 bits of data.
Figure 12a shows a read operation from the AD7711 where
RFS remains low for the duration of the data-word transmission.
With
DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the
DRDY line high. This rising edge of DRDY turns off
the serial data output.
Figure 12b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and
returns low again to access the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 12a, but Figure 12b has a number of additional times to
show timing relationships when
RFS returns high in the middle
of transferring a word.
RFS should return high during a low time of SCLK. On the
rising edge of
RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data-word
are read from the AD7711, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N+1) may appear on the data bus before
RFS goes high. When RFS returns low again, it activates the
SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as shown
in Figure 12a.
t20
SDATA (O)
SCLK (I)
RFS (I)
A0 (I)
DRDY (O)
t22
t24
t25
t26
t27
t29
t28
t23
t21
THREE-STATE
MSB
LSB
Figure 12a. External Clocking Mode, Output Data Read Operation
t20
SDATA (O)
SCLK (I)
RFS (I)
A0 (I)
DRDY (O)
t22
t24
t25
t26
t27
t24
t25
THREE-STATE
MSB
t30
t31
BIT N
BIT N+1
Figure 12b. External Clocking Mode, Output Data Read Operation (
RFS Returns High during Read Operation)
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