參數(shù)資料
型號(hào)： AD7713ARZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/28頁(yè)
文件大小： 0K
描述： IC ADC SIGNAL COND LC2MOS 24SOIC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 205
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 5.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)差分，單極；1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 778 (CN2011-ZH PDF)
REV. D
AD7713
–7–
PIN CONFIGURATION
PDIP, CERDIP, AND SOIC
1
SCLK
2
MCLK IN
3
MCLK OUT
4
A0
5
SYNC
6
MODE
7
AIN1(+)
10
AIN2(–)
9
AIN2(+)
8
AIN1(–)
11
STANDBY
12
AVDD
24
DGND
23
DVDD
22
SDATA
21
DRDY
20
RFS
19
TFS
18
AGND
15
REF IN(+)
16
RTD2
17
AIN3
14
REF IN(–)
13
RTD1
AD7713
TOP VIEW
(Not to Scale)
PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK be-
comes active when
RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns
high or when the device has completed transmission of an output word. When MODE is low, the device
is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a con-
tinuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a
noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data.
2
MCLK IN
Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A
crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is
nominally 2 MHz.
3
MCLK OUT
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
4A0Address Input. With this input low, reading and writing to the device is to the control register. With
this input high, access is to either the data register or the calibration registers.
5
SYNC
Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It
resets the nodes of the digital filter.
6
MODE
Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the
device is in its external clocking mode.
7
AIN1(+)
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The
AIN1(+) input is connected to an output current source that can be used to check that an external
transducer has burnt out or gone open circuit. This output current source can be turned on/off via the
control register.
8
AIN1(–)
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9
AIN2(+)
Analog Input Channel 2. Positive input of the programmable gain differential analog input.
10
AIN2(–)
Analog Input Channel 2. Negative input of the programmable gain differential analog input.
11
STANDBY
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 100
W.
12
AVDD
Analog Positive Supply Voltage, 5 V to 10 V.
13
RTD1
Constant Current Output. A nominal 200
A constant current is provided at this pin, which can be
used as the excitation current for RTDs. This current can be turned on or off via the control register.
14
REF IN(–)
Reference Input. The REF IN(–) can lie anywhere between AVDD and AGND, provided REF IN(+) is
greater than REF IN(–).
15
REF IN(+)
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF
IN(–). REF IN(+) can lie anywhere between AVDD and AGND.
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