參數(shù)資料
型號： AD7714YRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 8/40頁
文件大?。?/td> 0K
描述： IC ADC 24BIT SIGMA-DELTA 24TSSOP
標(biāo)準包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
配用： EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
AD7714
REV. C
–16–
MD2
MD1
MD0
Operating Mode (continued)
1
0
System-Offset Calibration; this activates system-offset calibration on the channel selected by CH2, CH1
and CH0 of the Communications Register. This is a one step calibration sequence and when complete
the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
DRDY output
or bit goes high when calibration is initiated and returns low when this system offset calibration is com-
plete and a new valid word is available in the data register. For this calibration type, the zero-scale cali-
bration is performed at the selected gain on the input voltage provided at the analog input during this
calibration sequence. This input voltage should remain stable for the duration of the calibration. The
full-scale calibration is performed at the selected gain on an internally generated VREF/Selected Gain.
1
0
1
Background Calibration; this activates background calibration on the channel selected by CH2, CH1
and CH0 of the Communications Register. If the background calibration mode is on, then the AD7714
provides continuous self-calibration of the shorted (zeroed) inputs. This calibration takes place as part
of the conversion sequence, extending the conversion time and reducing the word rate by a factor of six.
Its major advantage is that the user does not have to worry about recalibrating the offset of the device
when there is a change in the ambient temperature or supplies. In this mode, the zero-scale calibration
is performed at the selected gain on internally shorted (zeroed) inputs. The calibrations are interleaved
with normal conversions and the calibration registers of the device are automatically updated. Because
the background calibration does not perform full-scale calibrations, a self-calibration should be per-
formed before placing the part in the background calibration mode.
1
0
Zero-Scale Self-Calibration; this activates zero-scale self-calibration on the channel selected by CH2,
CH1 and CH0 of the Communications Register. This zero-scale self-calibration is performed at the
selected gain on internally shorted (zeroed) inputs. This is a one step calibration sequence and when
complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
DRDY
output or bit goes high when calibration is initiated and returns low when this zero-scale self-calibration
is complete and a new valid word is available in the data register.
1
Full-Scale Self-Calibration; this activates full-scale self-calibration on the channel selected by CH2,
CH1 and CH0 of the Communications Register. This full-scale self-calibration is performed at the
selected gain on an internally-generated VREF/Selected Gain. This is a one step calibration sequence and
when complete the part returns to Normal Mode with MD2, MD1 and MD0 returning to 0, 0, 0. The
DRDY output or bit goes high when calibration is initiated and returns low when this full-scale self-
calibration is complete and a new valid word is available in the data register.
G2
G1
G0
Gain Setting
0001
0012
0104
0118
10016
10132
11064
111128
BO
Burnout Current. A 0 in this bit turns off the on-chip burnout currents. This is the default (Power-On
or RESET) status of this bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one to the AIN(+) input and one to the AIN(–) input.
FSYNC
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic and
the calibration control logic are held in a reset state and the analog modulator is also held in its reset
state. When this bit goes low, the modulator and filter start to process data and a valid word is available
in 3
× 1/(output update rate), i.e., the settling time of the filter. This FSYNC bit does not affect the
digital interface and does not reset the
DRDY output if it is low.
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