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參數(shù)資料
型號(hào)： AD7714YRZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT SIGMA-DELTA 24SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
配用： EVAL-AD7714-3EBZ-ND - BOARD EVAL FOR AD7714
Parameter
Y Versions
Units
Conditions/Comments
LOGIC OUTPUTS (Continued))
VOH, Output High Voltage
DVDD – 0.6
V min
ISOURCE = 100 A with DVDD = 3 V. Except for MCLK OUT
12
Floating State Leakage Current
±10
A max
Floating State Output Capacitance13
9
pF typ
D
ata Output Coding
Binary
Unipolar Mode
Offset Binary
Bipolar Mode
TRANSDUCER BURNOUT14
Current
1
A nom
Initial Tolerance
±10
% typ
Drift
0.1
%/
°C typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit15
(1.05
× V
REF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Negative Full-Scale Calibration Limit15
–(1.05
× V
REF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Offset Calibration Limit16
–(1.05
× V
REF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
Input Span16
0.8
× V
REF/GAIN
V min
GAIN Is the Selected PGA Gain (Between 1 and 128)
(2.1
× V
REF)/GAIN
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage
+2.7 to +3.3 or
V
+4.75 to +5.25
V
For Specified Performance
DVDD Voltage
+2.7 to +5.25
V
For Specified Performance
Power Supply Currents
AVDD Current
AVDD = 3 V or 5 V. BST Bit of Filter High Register = 0
17, CLKDIS = 1
0.28
mA max
Typically 0.22 mA. BUFFER = 0 V. fCLK IN = 1 MHz or 2.4576 MHz
0.6
mA max
Typically 0.45 mA. BUFFER = DVDD. fCLK IN = 1 MHz or 2.4576 MHz
AVDD = 3 V or 5 V. BST Bit of Filter High Register = 1
17
0.5
mA max
Typically 0.38 mA. BUFFER = 0 V. fCLK IN = 2.4576 MHz
1.1
mA max
Typically 0.8 mA. BUFFER = DVDD. fCLK IN = 2.4576 MHz
DVDD Current
18
Digital I/Ps = 0 V or DVDD. External MCLK IN, CLKDIS = 1
0.080
mA max
Typically 0.06 mA. DVDD = 3 V. fCLK IN = 1 MHz
0.16
mA max
Typically 0.13 mA. DVDD = 5 V. fCLK IN = 1 MHz
0.18
mA max
Typically 0.15 mA. DVDD = 3 V. fCLK IN = 2.4576 MHz
0.35
mA max
Typically 0.3 mA. DVDD = 5 V. fCLK IN = 2.4576 MHz
Power Supply Rejection19
See Note 20
dB typ
Normal-Mode Power Dissipation18
AVDD = DVDD = +3 V. Digital I/Ps = 0 V or DVDD. External MCLK IN
BST Bit of Filter High Register = 017
1.05
mW max
Typically 0.84 mW. BUFFER = 0 V. fCLK IN = 1 MHz. BST Bit = 0
2.04
mW max
Typically 1.53 mW. BUFFER = +3 V. fCLK IN = 1 MHz. BST Bit = 0
1.35
mW max
Typically 1.11 mW. BUFFER = 0 V. fCLK IN = 2.4576 MHz. BST Bit = 0
2.34
mW max
Typically 1.9 mW. BUFFER = +3 V. fCLK IN = 2.4576 MHz. BST Bit = 0
Normal-Mode Power Dissipation
AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD. External MCLK IN
2.1
mW max
Typically 1.75 mW. BUFFER = 0 V. fCLK IN = 1 MHz. BST Bit = 0
3.75
mW max
Typically 2.9 mW. BUFFER = +5 V. fCLK IN = 1 MHz. BST Bit = 0
3.1
mW max
Typically 2.6 mW. BUFFER = 0 V. fCLK IN = 2.4576 MHz. BST Bit = 0
4.75
mW max
Typically 3.75 mW. BUFFER = +5 V. fCLK IN = 2.4576 MHz. BST Bit = 0
Standby (Power-Down) Current21
18
A max
External MCLK IN = 0 V or DVDD. Typically 9 A. VDD = +5 V
Standby (Power-Down) Current21
10
A max
External MCLK IN = 0 V or DVDD. Typically 4 A. VDD = +3 V
NOTES
1Temperature range is as follows: Y Version: –40
°C to +105°C.
2A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I to IV. This applies after calibration at the temperature of interest.
3Recalibration at any temperature will remove these drift errors.
4Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error—Unipolar Offset Error for unipolar ranges and Full-Scale Error—Bipolar Zero Error for
bipolar ranges.
7Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero-scale calibrations only were performed as is the case with background calibration.
8These numbers are guaranteed by design and/or characterization.
9The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.
10The input voltage range on the analog inputs is given here with respect to the voltage on the respective negative input of its differential or pseudo-differential pair. See Table VII for which
inputs form differential pairs.
11V
REF = REF IN(+) – REF IN(–).
12These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.
13Sample tested at +25
°C to ensure compliance.
14See Burnout Current section.
15After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD + 30 mV or go more negative than AGND – 30 mV. The offset calibration
limit applies to both the unipolar zero point and the bipolar zero point.
17For higher gains (
≥8) at f
CLK IN = 2.4576 MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD current and power dissipation will vary depending on the crystal or resonator
type (see Clocking and Oscillator Circuit section).
19Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter
notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20PSRR depends on gain.
Gain
1
2
4
8–128
AVDD = 3 V
86 dB
78 dB
85 dB
93 dB
AVDD = 5 V
90 dB
78 dB
84 dB
91 dB
21If the external master clock continues to run in standby mode, the standby current increases to 150
A typical with 5 V supplies and 75 A typical with 3.3 V supplies. When using a crystal
or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
AD7714Y
REV. C
–6–
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