AVDD = 5 V, DV
參數(shù)資料
型號: AD7715ARUZ-5REEL7
廠商: Analog Devices Inc
文件頁數(shù): 23/40頁
文件大小: 0K
描述: IC ADC 16BIT SIGMA-DELTA 16TSSOP
標準包裝: 1,000
位數(shù): 16
采樣率(每秒): 500
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 9.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極;1 個差分,雙極
配用: EVAL-AD7715-3EBZ-ND - BOARD EVALUATION FOR AD7715
AD7715
Rev. D | Page 3 of 40
SPECIFICATIONS
AD7715-5
AVDD = 5 V, DVDD = 3 V or 5 V, REF IN(+) = 2.5 V; REF IN() = AGND; fCLK IN = 2.4576 MHz, unless otherwise noted. All specifications
TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
16
Bits
Guaranteed by design; filter notch ≤ 60 Hz
Output Noise
See
Depends on filter cutoffs and selected gain
Integral Nonlinearity
±0.0015
% of FSR
Filter notch ≤ 60 Hz
Unipolar Offset Error2
See
Unipolar Offset Drift3
0.5
μV/°C
Bipolar Zero Error2
See
Bipolar Zero Drift3
0.5
μV/°C
Positive Full-Scale Error2, 4
See
Full-Scale Drift3, 5
0.5
μV/°C
Gain Error2, 6
See
Gain Drift3, 7
0.5
ppm of
FSR/°C
Bipolar Negative Full-Scale Error2
±0.0015
% of FSR
Typically ±0.0004%
Bipolar Negative Full-Scale Drift3
1
μV/°C
For gains of 1 and 2
0.6
μV/°C
For gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN unless noted
Input Common-Mode Rejection
(CMR)
90
dB
At dc; typically 102 dB
Normal-Mode 50 Hz Rejection8
98
dB
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
Normal-Mode 60 Hz Rejection8
98
dB
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
Common-Mode 50 Hz Rejection8
150
dB
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
Common-Mode 60 Hz Rejection8
150
dB
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
Common-Mode Voltage Range9
AGND
AVDD
V
AIN for the BUF bit of setup register = 0 and REF IN
Absolute AIN/REF IN Voltage8
AGND – 0.03
AVDD + 0.03
V
AIN for the BUF bit of setup register = 0 and REF IN
Absolute/Common-Mode AIN
AGND + 0.05
AVDD 1.5
V
BUF bit of setup register = 1
AIN DC Input Current8
1
nA
AIN Sampling Capacitance8
10
pF
AIN Differential Voltage Range10
0 to +VREF/GAIN11
nom
Unipolar input range (B/U bit of setup register = 1)
±VREF/GAIN
nom
Bipolar input range (B/U bit of setup register = 0)
AIN Input Sampling Rate, fS
GAIN × fCLKIN/64
For gains of 1 and 2
fCLK IN/8
For gains of 32 and 128
REF IN(+) REF IN() Voltage
2.5
V nom
±1% for specified performance; functional with
lower VREF
REF IN Input Sampling Rate, fS
fCLK IN/64
LOGIC INPUTS
Input Current
±10
μA
All Inputs Except MCLK IN
VINL, Input Low Voltage
0.8
V
DVDD = 5 V
VINL, Input Low Voltage
0.4
V
DVDD = 3.3 V
VINH, Input High Voltage
2.4
V
DVDD = 5 V
VINH, Input High Voltage
2.0
V
MCLK IN Only
VINL, Input Low Voltage
0.8
V
DVDD = 5 V
VINL, Input Low Voltage
0.4
V
DVDD = 3.3 V
VINH, Input High Voltage
3.5
V
DVDD = 5 V
VINH, Input High Voltage
2.5
V
DVDD = 3.3 V
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