參數(shù)資料
型號(hào): AD7723BSZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/32頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT SIGMA-DELTA 44MQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 1.2M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
配用: EVAL-AD7723CBZ-ND - BOARD EVALUATION FOR AD7723
AD7723
Rev. C | Page 26 of 32
The master device is selected by setting TSI to a logic low and
connecting its FSO to DOE. The slave device is selected with its
TSI pin tied high and both its FSI and DOE controlled from the
master’s FSO. Since the FSO of the master controls the DOE
input of both the master and slave, one ADC’s SDO is active
while the other is high impedance (Figure 46). When the master
transmits its conversion result during the first 16 SCO cycles of
a data transmission frame, the low level on DOE sets the slave’s
SDO high impedance. Once the master completes transmitting
its conversion data, its FSO goes high and triggers the slave’s FSI
to begin its data transmission frame.
Since FSO pulses are gated by the release of FSI (going low) and
the FSI of the slave device is held high during its data
transmission, the FSO from the master device must be used for
connection to the host processor.
CLKIN
FSI
SCO
FSO (MASTER)
FSI (SLAVE)
DOE (MASTER AND SLAVE)
SDO (MASTER)
SDO (SLAVE)
D1
D0
D15
D14
D15
D14
D1
D0
t11
t12
t13
t9
t15
t16
t15
01186-046
Figure 46. Serial Mode 1 Timing for Two-Channel Multiplexed Operation
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AD7723BSZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
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