參數(shù)資料
型號(hào)： AD7760BSVZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/37頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 2.5MSPS 64TQFP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 24
采樣率（每秒）： 2.5M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 958mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-TQFP-EP（10x10）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，單極；1 個(gè)差分，雙極
AD7760
Rev. A | Page 20 of 36
MODULATOR DATA OUTPUT MODE INTERFACE
The AD7760 can be configured in modulator data output mode
(bypassing the default decimation filtering) by writing 0 to each
of the bits contained in Control Register 1: BYP F1, BYP F3,
and DEC [2:0]. This will bypass all digital decimation filtering
offered by the AD7760. See the AD7760 Registers section for
further details.
When the AD7760 is operating in modulator data output mode,
a different parallel interfacing scheme than that used for config-
urations, where the AD7760’s data output is filtered is necessary.
The data output rate depends on the clock divider ratio that is
used. When the CDIV bit in Control Register 2 is set to logic
high, data is output at the MCLK frequency. If the CDIV bit is
set to logic low, data is output at a frequency of MCLK/2. See
CLOCK DIVIDE-BY-1 MODE (CDIV = 1)
When obtaining data from the AD7760 in modulator output
mode, both the RD/WR and CS lines must be held low. This
brings the data bus out of its high impedance state. Figure 43
shows the timing diagram for reading data in the modulator data
output mode when operating with CDIV = 1 (that is, ICLK =
MCLK). A DRDY pulse is generated for each word. The data on
each of the 16 data output pins, D [15:0], is valid on the rising
edge of the DRDY pulse. The DRDY pulse can be used to latch
the modulator data into a FIFO or as a DMA control signal. Shortly
after the RD/WR and CS lines return high, the AD7760 stops
outputting data and the data bus returns to high impedance.
CLOCK DIVIDE-BY-2 MODE (CDIV = 0)
When operating in modulator output mode with CDIV = 0
(that is, ICLK = MCLK/2), the frequency of the DRDY signal
created is half that of the MCLK frequency input to the device.
The timing scheme that is used when CDIV = 0 depends on the
number of MCLK cycles that occur between RESET and SYNC.
If the number of MCLK cycles (n) between the rising edge of
RESET and the rising edge of SYNC (see Figure 44) is an even
value, use the interface timing shown in Figure 43. If n is an odd
value, use the interface timing shown in Figure 45.
t9
t10
t14
t11
t12
t13
DRDY
CS, RD/WR
D[0:15]
INVALID DATA
MOD DATA M
MOD DATA M + 1
MOD D...
04
97
5-
0
50
Figure 43. AD7760 Modulator Output Mode (CDIV = 1) and (CDIV = 0, n is even)
MCLK
RESET
SYNC
n×
tMCLK
04
975
-05
1
Figure 44. AD7760 Relative Timing Between RESET and SYNC in Modulator Output Mode CDIV = 0
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