參數(shù)資料
型號: AD7766BRUZ-2-RL7
廠商: Analog Devices Inc
文件頁數(shù): 15/25頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 32KSPS SAR 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 32k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 18mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
配用: EVAL-AD7766EDZ-ND - BOARD EVAL AD7766 128KSPS 108DB
EVAL-AD7766-2EDZ-ND - BOARD EVAL AD7766-2 32KSPS 114DB
EVAL-AD7766-1EDZ-ND - BOARD EVAL AD7766-1 64KSPS 111DB
AD7766
Rev. C | Page 21 of 24
ANTIALIASING
The AD7766/AD7766-1/AD7766-2 sample the analog input
at a maximum rate of 1.024 MHz. The on-board digital filter
provides up to 100 dB attenuation for any possible aliasing
frequency in the range from the beginning of the filter stop
band (0.547 × ODR) to where the image of the digital filter pass
band occurs. This occurs at fMCLK minus the filter stop band
(fMCLK 0.547 × ODR), as shown in Figure 42.
06
44
9-
2
31
DIGITAL FILTER 100dB
ANTIALIAS PROTECTION
fMCLK
BAND OF INTEREST
fMCLK – (0.547 × ODR)
FIRST IMAGE POINT
DIGITAL FILTER
IMAGE AT
fMCLK
Figure 42. AD7766/AD7766-1/AD7766 Spectrum
Table 9 shows the attenuation achieved by various orders of
front-end antialias filters prior to the signal entering the AD7766/
AD7766-1/AD7766-2 at the image of the digital filter stop band,
which is 1.024 MHz 0.547 × ODR.
Table 9. Antialias Filter Order
Model
Filter Order
Attenuation at
1.024 MHz – 0.547 × ODR
AD7766
First
27 dB
Second
50 dB
Third
70 dB
AD7766-1
First
33 dB
Second
62 dB
Third
89 dB
AD7766-2
First
38 dB
Second
74 dB
Third
110 dB
The AD7764 and AD7765 ∑-Δ devices are available to
customers that require extra antialias protection. These devices
sample the signal internally at a rate of 20 MHz to achieve up to
a maximum of 156 kHz or 312 kHz output data rate. This
means that the first alias point of these devices when run at the
maximum speeds is 19.921 MHz and 19.843 MHz, respectively.
POWER DISSIPATION
The AD7766/AD7766-1/AD7766-2 offer exceptional perform-
ance at ultralow power. Figure 43, Figure 44, and Figure 45
show how the current consumption of the AD7766, AD7766-1,
and AD7766-2 scales with the MCLK frequency applied to the
device. Both the digital and analog currents scale as the MCLK
frequency is reduced. The actual throughput equals the MCLK
frequency applied divided by the decimation rate employed by
the device in use. For instance, operating the AD7766 device with
an MCLK of 800 kHz results in an output data rate of 100 kHz
due to the decimate-by-8 filtering.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1000k
900k
800k
700k
600k
500k
400k
300k
200k
100k
CUR
RE
N
T
(
m
A)
FREQUENCY (Hz)
06
44
9-
22
6
IREF
AIDD
DIDD
Figure 43. AD7766 Current vs. MCLK Frequency
2.5
2.0
1.5
1.0
0.5
0
1000k
900k
800k
700k
600k
500k
400k
300k
200k
100k
CUR
RE
N
T
(
m
A)
FREQUENCY (Hz)
06
44
9-
22
7
IREF
AIDD
DIDD
Figure 44. AD7766-1 Current vs. MCLK Frequency
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1000k
900k
800k
700k
600k
500k
400k
300k
200k
100k
CUR
RE
NT
(
m
A
)
FREQUENCY (Hz)
064
49
-2
28
IREF
AIDD
DIDD
Figure 45. AD7766-2 Current vs. MCLK Frequency
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