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參數(shù)資料
| 型號： | AD7766BRUZ-2-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 32KSPS SAR 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 32k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 18mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | EVAL-AD7766EDZ-ND - BOARD EVAL AD7766 128KSPS 108DB EVAL-AD7766-2EDZ-ND - BOARD EVAL AD7766-2 32KSPS 114DB EVAL-AD7766-1EDZ-ND - BOARD EVAL AD7766-1 64KSPS 111DB |
AD7766
Rev. C | Page 15 of 24
THEORY OF OPERATION
The AD7766/AD7766-1/AD7766-2 operate using a fully
differential analog input applied to a successive approximation
(SAR) core. The output of the oversampled SAR is filtered using
a linear-phase digital FIR filter. The fully filtered data is output
in a serial format, with the MSB being clocked out first.
AD7766/AD7766-1/AD7766-2 TRANSFER
FUNCTION
The conversion results of the AD7766/AD7766-1/AD7766-2
are output in a twos complement, 24-bit serial format. The fully
differential inputs VIN+ and VIN are scaled by the AD7766/
AD7766-1/AD7766-2 relative to the reference voltage input
06
44
9-
01
2
100 ... 000
100 ... 001
111 ... 110
111 ... 111
000 ... 000
000 ... 001
000 ... 010
011 ... 110
011 ... 111
24
-B
IT
O
U
T
P
U
T
24 BITS
TWOS
COMPLEMENT
VIN+ = 0V
VIN+ = VREF+ – 1LSB
VIN– = VREF+ – 1LSB
VIN– = 0V
VIN+ =
VREF+
2
VIN– =
VREF+
2
Figure 28. AD7766/AD7766-1/AD7766-2 Transfer Function
CONVERTER OPERATION
Internally, the input waveform applied to the SAR core is
converted and an equivalent digital word is output to the digital
filter at a rate equal to MCLK. By employing oversampling, the
quantization noise of the converter is spread across a wide
bandwidth from 0 to fMCLK. This means that the noise energy
contained in the signal band of interest is reduced (see
QUANTIZATION NOISE
BAND OF INTEREST
fMCLK/2
06
44
9-
2
13
Figure 29. Quantization Noise
DIGITAL FILTER CUTOFF FREQUENCY
fMCLK/2
BAND OF INTEREST
0
64
49
-2
14
Figure 30. Digital Filter Cutoff Frequency
The digital filtering that follows the converter output acts to
remove the out-of-band quantization noise (see Figure 30). This
also has the effect of reducing the data rate from fMCLK at the
input of the filter to fMCLK/8, fMCLK/16, or fMCLK/32 at the digital
output, depending on which model of the device is being used.
The digital filter consists of three separate filter blocks. Figure 31
shows the three constituent blocks of the filter. The order of
decimation of the first filter block is set as 2, 4, or 8. The
remaining sections each operate with a decimation of 2.
06
44
9-
0
1
9
STAGE 1
STAGE 2
DIGITAL FILTER
STAGE 3
SINC FILTER
FIR FILTER
DEC × (2 × n)
DEC × 2
DATA
STREAM
SDO
Figure 31. FIR Filter Stages
(n = 1 for AD7766, n = 2 for AD7766-1, n = 4 for AD7766-2)
Table 6 shows the three available models of the AD7766, listing
the change in output data rate relative to the order of decimation
rate implemented. This brings into focus the trade-off that exists
between extra filtering and reduction in bandwidth, whereby
using a filter option with a larger decimation rate increases the
noise performance while decreasing the usable input bandwidth.
Table 6. AD7766 Models
Model
Decimation Rate
Output Data Rate (ODR)
AD7766
8
128 kHz
AD7766-1
16
64 kHz
AD7766-2
32
32 kHz
Note that the output data rates shown in Table 6 are realized
when using the maximum MCLK input frequency of 1.024 MHz.
The output data rate scales linearly with the MCLK frequency,
as does the digital power dissipated in the device.
The settling time of the filter implemented on the AD7766,
AD7766-1, and AD7766-2 is related to the length of the filter
employed. The response of the filter in the time domain sets the
filter settling time. Table 7 shows the filter settling times of the
AD7766/AD7766-1/AD7766-2.
The frequency responses of the digital filters on the AD7766,
and Figure 34, respectively. At the Nyquist frequency (output
data rate/2), the digital filter provides 6 dB of attenuation. In each
case, the filter provides stop-band attenuation of 100 dB and
pass-band ripple of ±0.005 dB.
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| AD7766BRUZ-RL7 | 功能描述:IC ADC 24BIT 128KSPS SAR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7767 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs |
| AD7767BRUZ | 功能描述:ADC 24BIT 128KSPS SAR 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7767BRUZ-1 | 功能描述:ADC 24BIT 64KSPS SAR 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7767BRUZ-1-RL7 | 功能描述:ADC 24BIT 10.5MW 64KSPS 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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