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參數(shù)資料
| 型號： | AD7789BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT LP 10-MSOP |
| 標準包裝： | 50 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 16.6 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
AD7788/AD7789
Rev. B | Page 13 of 20
MODE REGISTER
(RS1, RS0 = 0, 1; Power-On/Reset = 0x02)
The mode register is an 8-bit register from which data can be read from or written to. This register is used to configure the ADC for
range, to set unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 11 outlines the
bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7
denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the
setup register resets the modulator and filter, and sets the RDY bit.
MSB
LSB
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
MD1[0]
MD0[0]
0[0]
U/B[0]
1[1]
0[0]
Table 11. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR7 to MR6
MD1 to MD0
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. DOUT/ RDY goes low when a conversion is complete. The user can read these
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT/ RDY line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. In single
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up (which takes 1 ms) and performs a single
conversion, requiring a duration of 2/fADC. The conversion result is placed in the data register, DOUT/ RDY
goes low, and the ADC returns to power-down mode. The conversion remains in the data register and
DOUT/ RDY remains active (low) until the data is read or another conversion is performed (see Table 12).
MR5 to MR3
0
These bits must be programmed with a Logic 0 for correct operation.
MR2
U/B
Unipolar/Bipolar Bit. Set by user to enable unipolar coding; that is, zero differential input results in
000…000 output, and a full-scale differential input results in 111…111 output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input results in an output code of 000…000, zero
differential input results in an output code of 100…000, and a positive full-scale differential input results in
an output code of 111…111.
MR1
1
This bit must be programmed with a Logic 1 for correct operation.
MR0
0
This bit must be programmed with a Logic 0 for correct operation.
Table 12. Operating Modes
MD1
MD0
Mode
0
Continuous conversion mode (default)
0
1
Reserved
1
0
Single conversion mode
1
Power-down mode
DATA REGISTER
(RS1, RS0 = 1, 1; Power-On/Reset = 0x0000 for the AD7788 and 0x000000 for the AD7789)
The conversion result from the ADC is stored in this data register. This is a read only register. On completion of a read operation from
this register, the RDY bit/pin is set.
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