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參數(shù)資料
| 型號： | AD7791BRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
Data Sheet
AD7791
Rev. A | Page 19 of 20
Reference voltage sources like those recommended above
(e.g., ADR391) will typically have low output impedances and
are, therefore, tolerant to having decoupling capacitors on
REFIN(+) without introducing gain errors in the system.
Deriving the reference input voltage across an external resistor
will mean that the reference input sees a significant external
source impedance. External decoupling on the REFIN pins
would not be recommended in this type of circuit
configuration.
VDD MONITOR
Along with converting external voltages, the analog input chan-
nel can be used to monitor the voltage on the VDD pin. When
the CH1 and CH0 bits in the communications register are set to
1, the voltage on the VDD pin is internally attenuated by 5 and
the resultant voltage is applied to the ∑- modulator using an
internal 1.17 V reference for analog to digital conversion. This
is useful because variations in the power supply voltage can be
monitored.
GROUNDING AND LAYOUT
Since the analog inputs and reference inputs of the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode rejec-
tion of the part will remove common-mode noise on these
inputs. The digital filter will provide rejection of broadband
noise on the power supply, except at integer multiples of the
modulator sampling frequency. The digital filter also removes
noise from the analog and reference inputs, provided that these
noise sources do not saturate the analog modulator. As a result,
the AD7791 is more immune to noise interference than a con-
ventional high resolution converter. However, because the
resolution of the AD7791 is so high, and the noise levels from
the AD7791 are so low, care must be taken with regard to
grounding and layout.
The printed circuit board that houses the AD7791 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes because it gives
the best shielding.
It is recommended that the AD7791’s GND pin be tied to the
AGND plane of the system. In any layout, it is important that
the user keep in mind the flow of currents in the system, ensur-
ing that the return paths for all currents are as close as possible
to the paths the currents took to reach their destinations. Avoid
forcing digital currents to flow through the AGND sections of
the layout.
The AD7791’s ground plane should be allowed to run under the
AD7791 to prevent noise coupling. The power supply lines to
the AD7791 should use as wide a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching signals such as clocks should
be shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects of feed-
through through the board. A microstrip technique is by far the
best, but it is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes, while signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. VDD should be decoupled with 10 F tantalum in parallel
with 0.1 F capacitors to GND. To achieve the best from these
decoupling components, they should be placed as close as
possible to the device, ideally right up against the device. All
logic chips should be decoupled with 0.1 F ceramic capacitors
to DGND.
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