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參數(shù)資料
| 型號： | AD7796BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SIG-DEL 1CH 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 123 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7796EBZ-ND - BOARD EVALUATION FOR AD7796 |
AD7796/AD7797
Rev. A | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
1
2
3
4
5
6
7
8
CLK
CS
NC
AIN(–)
AIN(+)
SCLK
NC
16
15
14
13
12
11
10
9
DOUT/RDY
DVDD
AVDD
REFIN(–)
REFIN(+)
NC
GND
DIN
TOP VIEW
(Not to Scale)
AD7796/
AD7797
06
08
3-
00
5
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous
with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the ADC in smaller batches of data.
2
CLK
Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be
disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a common
clock, allowing simultaneous conversions to be performed.
3
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
4
NC
No Connect.
5
AIN(+)
Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN().
6
AIN()
Analog Input. AIN() is the negative terminal of the differential analog input pair AIN(+)/AIN().
7
NC
No Connect.
8
NC
No Connect.
9
REFIN(+)
Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(–).
REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN()) is
2.5 V, but the parts function with a reference of 0.1 V to AVDD.
10
REFIN()
Negative Reference Input/Analog Input. REFIN() is the negative reference input for REFIN. This reference input
can lie anywhere between GND and AVDD 0.1 V.
11
NC
No Connect.
12
GND
Ground Reference Point.
13
AVDD
Supply Voltage, 2.7 V to 5.25 V.
14
DVDD
Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is
between 2.7 V and 5.25 V. The DVDD voltage is independent of the voltage on AVDD; therefore, AVDD can equal 5 V
with DVDD at 3 V or vice versa.
15
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin
to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip
data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion
of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word
information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
16
DIN
Serial Data Input. This serial data input accesses the input shift register on the ADC. Data in this shift register is
transferred to the control registers within the ADC; the register selection bits of the communication register
identify the appropriate register.
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