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參數(shù)資料
| 型號： | AD7796BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SIG-DEL 1CH 16TSSOP |
| 標準包裝： | 96 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 123 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.6mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7796EBZ-ND - BOARD EVALUATION FOR AD7796 |
AD7796/AD7797
Rev. A | Page 13 of 24
Table 13. Operating Modes
MD2
MD1
MD0
Mode
0
Continuous Conversion Mode (default). In continuous conversion mode, the ADC continuously performs
conversions and places the result in the data register. RDY goes low when a conversion is complete. The user can
read these conversions by placing the device in continuous read mode, whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the
conversion by writing to the communication register. After a power-on, channel change, or write to the mode or
configuration register, the first conversion is available after a period of 2/fADC, while subsequent conversions are
available at a frequency of fADC.
0
1
Single Conversion Mode. When single conversion mode is selected, the ADC powers up and performs a single
conversion. The oscillator requires 1 ms to power up and settle. The ADC then performs the conversion, which takes
a time of 2/fADC. The conversion result is placed in the data register, RDY goes low, and the ADC returns to power-
down mode. The conversion remains in the data register and RDY remains active (low) until the data is read or
another conversion is performed.
0
1
0
Idle Mode. In idle mode, the ADC filter and modulator are held in a reset state although the modulator clocks are
still provided.
0
1
Power-Down Mode. In power-down mode, all the AD7796/AD7797 circuitry is powered down, including the
burnout currents and CLKOUT circuitry.
1
0
Internal Zero-Scale Calibration. An internal short is automatically connected to the channel. A calibration takes
two conversion cycles to complete. RDY goes high when the calibration is initiated and returns low when the
calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is
placed in the offset register.
1
0
1
Reserved.
1
0
System Zero-Scale Calibration. Users should connect the system zero-scale input to the channel input pins.
A system offset calibration takes two conversion cycles to complete. RDY goes high when the calibration is
initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.
The measured offset coefficient is placed in the offset register.
1
System Full-Scale Calibration. Users should connect the system full-scale input to the channel input pins.
A calibration takes two conversion cycles to complete. RDY goes high when the calibration is initiated and returns
low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-
scale coefficient is placed in the full-scale register.
Table 14. Update Rates Available
FS3
FS2
FS1
FS0
fADC (Hz)
tSETTLE (ms)
Rejection @ 50 Hz/60 Hz (Internal Clock)
0
X
0
1
X
0
1
0
X
0
1
123
16
0
1
0
62
32
0
1
0
1
50
40
0
1
0
X
0
1
33.2
60
1
0
X
1
0
1
16.7
120
80 dB (50 Hz only)
1
0
1
0
16.7
120
65 dB (50 Hz and 60 Hz)
1
0
1
12.5
160
66 dB (50 Hz and 60 Hz)
1
0
10
200
69 dB (50 Hz and 60 Hz)
1
0
1
8.33
240
70 dB (50 Hz and 60 Hz)
1
0
6.25
320
72 dB (50 Hz and 60 Hz)
1
4.17
480
74 dB (50 Hz and 60 Hz)
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