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| 型號： | AD7801BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT PARALLEL INP 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 設(shè)置時間： | 1.2µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 12.9mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 833k |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
AD7801
–10–
REV. 0
Figure 27 shows a typical setup for the AD7801 when using its
internal reference. The internal reference is selected by tying the
REFIN pin to VDD. Internally in the reference section there is a
reference detect circuit that will select the internal VDD/2 based
on the voltage connected to the REFIN pin. If REFIN is within
a threshold voltage of a PMOS device (approximately 1 V) of
VDD the internal reference is selected. When the REFIN voltage
is more than 1 V below VDD, the externally applied voltage at
this pin is used as the reference for the DAC. The internal
reference on the AD7801 is VDD/2, the output current to
voltage converter within the AD7801 provides a gain of two.
Thus the output range of the DAC is from 0 V to VDD, based on
Table I.
DATA BUS
CONTROL
INPUTS
AD7801
CS WR
LDAC
VOUT
D7-D0
CLR
PD
VDD
REF IN
VDD = 3V TO 5V
VDD
AGND DGND
10 F
0.1 F
Figure 27. Typical Configuration Selecting the Internal
Reference
Figure 28 shows a typical setup for the AD7801 when using an
external reference. The reference range for the AD7801 is from
1 V to V
DD/2 V. Higher values of reference can be incorporated
but will saturate the output at both the top and bottom end of
the transfer function. There is a gain of two from input to output
on the AD7801. Suitable references for 5 V operation are the
AD780 and REF192. For 3 V operation a suitable external
reference would be the AD589 a 1.23 V bandgap reference.
DATA BUS
CONTROL
INPUTS
AD7801
CS WR LDAC
VOUT
D7-D0
CLR
PD
VDD
REF IN
VDD = 3V TO 5V
VDD
AGND DGND
10 F
0.1 F
EXT REF V
OUT
VIN
GND
AD780/REF192 WITH VDD = 5V
OR
AD589 WITH VDD = 3V
Figure 28. Typical Configuration Using An External
Reference
MICROPROCESSOR INTERFACING
AD7801–ADSP-2101/ADSP-2103 Interface
Figure 29 shows an interface between the AD7801 and the ADSP-
2101/ADSP-2103. The fast interface timing associated with the
AD7801 allows easy interface to the ADSP-2101/ADSP-2103.
LDAC is permanently tied low in this circuit so the DAC
output is updated on the rising edge of the
WR signal.
Data is loaded to the AD7801 input register using the following
ADSP-21xx instruction.
DM(DAC) = MR0
MR0 = ADSP-21xx MR0 Register.
DAC = Decoded DAC Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
DMA14
DMA0
DMS
WR
DMD15
DMD0
ADSP-2101*/
ADSP-2103*
Figure 29. AD7801–ADSP-2101/ADSP-2103 Interface
AD7801–TMS320C20 Interface
Figure 30 shows an interface between the AD7801 and the
TMS320C20. Data is loaded to the AD7801 using the following
instruction:
OUT DAC, D
DAC = Decoded DAC Address.
D = Data Memory Address.
ADDR
DECODE
EN
ADDRESS BUS
AD7801*
CS
LDAC
WR
DB7
DB0
DATA BUS
*ADDITIONAL CIRCUITRY OMITTED FOR CLARITY.
A15
A0
IS
STRB
D15
D0
TMS320C20
R/
W
Figure 30. AD7801–TMS320C20 Interface
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