參數(shù)資料
型號： AD7805BNZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/28頁
文件大小： 0K
描述： IC DAC 10BIT QUAD PARALLEL 28DIP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 13
設(shè)置時(shí)間： 1.5µs
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 66mW
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 28-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 28-PDIP
包裝： 管件
輸出數(shù)目和類型： 8 電壓，雙極
采樣率（每秒）： 667k
AD7804/AD7805/AD7808/AD7809
REV. A
–18–
OFFSET BINARY CODING
Table VIII shows the offset binary transfer function for the Main
DAC.
Table VIII. Offset Binary Code Table for Main DAC
Digital Inputs
Analog Output
MSB . . . LSB
1111111111
VBIAS+1.875
× V
BIAS(1023–512)/1024
1111111110
VBIAS+1.875
× V
BIAS(1022–512)/1024
1000000001
VBIAS+1.875
× V
BIAS/1024
1000000000
VBIAS
0111111111
VBIAS+1.875
× V
BIAS(511–512)/1024
0000000001
VBIAS+1.875
× V
BIAS(1–512)/1024
0000000000
VBIAS/16
NOTE: The span range is (30/16)
× V
BIAS = 1.875 × VBIAS
VBIAS
DAC
OUTPUT
VOLTAGE
000
001
DAC INPUT CODE
1FF 200 201
3FE
3FF
VBIAS
16
31
16 VBIAS
Figure 25. Main DAC Output Voltage vs. DAC Input Codes
(HEX) for Offset Binary Coding
Figure 25 shows the Main DAC transfer function when offset
binary coding is used. With offset binary coding selected the
output voltage can be calculated as follows:
VOUT' = VBIAS + 1.875
× V
BIAS
× ((NA-512)/1024)
where NA is the decimal equivalent of the offset binary input
code. NA ranges from 0 to 1023.
Table IX shows the offset binary transfer function for the Sub
DAC. Figure 26 shows the Sub DAC transfer function for
offset binary coding. Any Sub DAC output voltage can be
expressed as:
VOUT" = VBIAS/16
× [(NB-128)/256]
where NB is the decimal equivalent of the offset binary input
code. NB ranges from 0 to 255.
Table VI and Figure 22 show the analog outputs available for
the above configuration. The following is the procedure re-
quired if the complete transfer function needs to be offset
around the VBIAS point. Table VII and Figure 23 show the ana-
log output variations available from the Sub DAC.
System Control Register Write:
MODE = 0, address inputs (A2, A1, A0) are don’t cares.
Write 020 Hex
Configure part for 10-bit parallel, twos
complement coding, normal operation
Channel Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 091 Hex
Internal VDD/2 selected as VBIAS for
DAC, and any DAC data writes that
follow are to the Sub DAC.
DAC Data Register Write:
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XX Hex
With MODE = 1 all data writes are to
the selected DACs Sub DAC. XX is the
required data. 7F Hex will give zero scale
and 80 Hex will give full scale from the
Sub DAC.
Channel Control Register Write:
MODE = 0, address inputs (A2, A1, A0) select desired channel.
Write 011 Hex
Internal VDD/2 selected as VBIAS for
DAC, and any DAC data writes that
follow are to the Main DAC.
DAC Data Register Write:
MODE = 1, address inputs (A2, A1, A0) select desired channel.
Write XXX Hex With MODE = 1 all data writes are to
the selected Main DAC. XXX is the
required data. 1FF Hex will give zero
scale and 200 Hex will give full scale
from the DAC.
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